Add icmp instruction

fox32-arch · May 24, 2024 · 2e38a14 · 2e38a14
1 parent d69cc85
commit 2e38a14
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Showing 4 changed files with 11 additions and 4 deletions.
diff --git a/docs/cpu.md b/docs/cpu.md
@@ -110,7 +110,7 @@ data.16 0x8700 data.8 20 data.8 1
 | 0x04  | SLA    | src+tgt  | 8/16/32 | shift left
 | 0x05  | SRA    | src+tgt  | 8/16/32 | shift right arithmetic (with sign extension)
 | 0x06  | BSE    | src+tgt  | 8/16/32 | bit set
-| 0x07  | CMP    | src+tgt  | 8/16/32 | compare
+| 0x07  | CMP    | src+tgt  | 8/16/32 | unsigned compare
 | 0x08  | JMP    | src      |      32 | absolute jump
 | 0x09  | RJMP   | src      |      32 | relative jump
 | 0x0A  | PUSH   | src      | 8/16/32 | push value to stack
@@ -148,6 +148,7 @@ data.16 0x8700 data.8 20 data.8 1
 | 0x33  | NOT    | src      | 8/16/32 | bitwise NOT
 | 0x34  | IDIV   | src+tgt  | 8/16/32 | divide (signed)
 | 0x35  | IREM   | src+tgt  | 8/16/32 | remainder (signed)
+| 0x37  | ICMP   | src+tgt  | 8/16/32 | signed compare
 | 0x39  | RTA    | src+tgt  |      32 | calculate address relative to instruction pointer
 | 0x3A  | RETI   | none     |      32 | return from interrupt
 | 0x3D  | FLP    | src      |      32 | flush page from TLB

diff --git a/docs/encoding.md b/docs/encoding.md
@@ -19,7 +19,7 @@ If the instruction doesn't allow variable sizes or a size was not specified, set
 | 0-  | NOP  | ADD[.8,16,32] | MUL[.8,16,32] | AND[.8,16,32] | SLA[.8,16,32]  | SRA[.8,16,32]  | BSE[.8,16,32] | CMP[.8,16,32]  | JMP  | RJMP  | PUSH[.8,16,32] | IN  | ISE | MSE |     |     |
 | 1-  | HALT | INC[.8,16,32] |               | OR[.8,16,32]  | IMUL[.8,16,32] | SRL[.8,16,32]  | BCL[.8,16,32] | MOV[.8,16,32]  | CALL | RCALL | POP[.8,16,32]  | OUT | ICL | MCL |     |     |
 | 2-  | BRK  | SUB[.8,16,32] | DIV[.8,16,32] | XOR[.8,16,32] | ROL[.8,16,32]  | ROR[.8,16,32]  | BTS[.8,16,32] | MOVZ[.8,16,32] | LOOP | RLOOP | RET            |     | INT | TLB |     |     |
-| 3-  |      | DEC[.8,16,32] | REM[.8,16,32] | NOT[.8,16,32] | IDIV[.8,16,32] | IREM[.8,16,32] |               |                |      | RTA   | RETI           |     |     | FLP |     |     |
+| 3-  |      | DEC[.8,16,32] | REM[.8,16,32] | NOT[.8,16,32] | IDIV[.8,16,32] | IREM[.8,16,32] |               | ICMP[.8,16,32] |      | RTA   | RETI           |     |     | FLP |     |     |
 
 # Condition table
 |       |        |                                               |
@@ -51,4 +51,4 @@ If the instruction doesn't allow variable sizes or a size was not specified, set
 | 0b11 | immediate (pointer) |
 
 # Register Pointer Offset
-The off field indicates that each operand of type 0b01 (register pointer) has an 8 bit immediate.  This immediate is added to the value of the register before derefencing.
+The off field indicates that each operand of type 0b01 (register pointer) has an 8 bit immediate.  This immediate is added to the value of the register before derefencing.
diff --git a/docs/instructions.md b/docs/instructions.md
@@ -10,7 +10,8 @@ description of the fox32 CPU and instruction encoding details, see [cpu.md](./cp
 ### SUB: subtract
 ### INC: increment (add 1/2/4/8)
 ### DEC: decrement (subtract 1/2/4/8)
-### CMP: compare
+### CMP: unsigned compare
+### ICMP: signed compare
 ### AND: bitwise AND
 ### OR: bitwise OR
 ### NOT: bitwise NOT

diff --git a/src/cpu.c b/src/cpu.c
@@ -96,6 +96,7 @@ enum {
     OP_NOT   = 0x33,
     OP_IDIV  = 0x34,
     OP_IREM  = 0x35,
+    OP_ICMP  = 0x37,
     OP_RTA   = 0x39,
     OP_RETI  = 0x3A,
     OP_FLP   = 0x3D,
@@ -246,6 +247,7 @@ static const asm_iinfo_t asm_iinfos[256] = {
     [OP_NOT  ] = { "NOT  ", 1 },
     [OP_IDIV ] = { "IDIV ", 2 },
     [OP_IREM ] = { "IREM ", 2 },
+    [OP_ICMP ] = { "ICMP ", 2 },
     [OP_RTA  ] = { "RTA  ", 2 },
     [OP_RETI ] = { "RETI ", 0 },
     [OP_FLP  ] = { "FLP  ", 1 }
@@ -1110,6 +1112,9 @@ static void vm_execute(vm_t *vm) {
         case OP(SZ_BYTE, OP_CMP): VM_IMPL_CMP(SIZE8, uint8_t, vm_source8);
         case OP(SZ_HALF, OP_CMP): VM_IMPL_CMP(SIZE16, uint16_t, vm_source16);
         case OP(SZ_WORD, OP_CMP): VM_IMPL_CMP(SIZE32, uint32_t, vm_source32);
+        case OP(SZ_BYTE, OP_ICMP): VM_IMPL_CMP(SIZE8, int8_t, vm_source8);
+        case OP(SZ_HALF, OP_ICMP): VM_IMPL_CMP(SIZE16, int16_t, vm_source16);
+        case OP(SZ_WORD, OP_ICMP): VM_IMPL_CMP(SIZE32, int32_t, vm_source32);
 
         case OP(SZ_BYTE, OP_BTS): VM_IMPL_BTS(SIZE8, uint8_t, vm_source8);
         case OP(SZ_HALF, OP_BTS): VM_IMPL_BTS(SIZE16, uint16_t, vm_source16);