Merge pull request #20 from eiowlta/main

Register Pointer Offsets, optional low hanging optimization, fixedwidth shift/bit operands
fox32-arch · Jul 23, 2023 · 7777dfd · 7777dfd
2 parents e9780d0 + fac2865
commit 7777dfd
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diff --git a/docs/cpu.md b/docs/cpu.md
@@ -162,6 +162,7 @@ data.16 0x8700 data.8 20 data.8 1
 |  2    | word (32 bits)
 |  3    | reserved
 
+For SLA, SRA, SRL, ROR, ROL, BCL, BSE, BTS, src immediates are fixed to 8 bits
 
 ## Interrupts and Exceptions
 

diff --git a/docs/encoding.md b/docs/encoding.md
@@ -1,7 +1,7 @@
 # Encoding
 ```
-size instr  . cond dest src <src>          <dest>
-xx   xxxxxx 0 xxx  xx   xx  <8,16,32 bits> <8,16,32 bits>
+size instr  off cond dest src <src>          <srcoff> <dest>         <dstoff>
+xx   xxxxxx x   xxx  xx   xx  <8,16,32 bits> <8 bits> <8,16,32 bits> <8 bits>
 ```
 
 
@@ -49,3 +49,6 @@ If the instruction doesn't allow variable sizes or a size was not specified, set
 | 0b01 | register (pointer)  |
 | 0b10 | immediate           |
 | 0b11 | immediate (pointer) |
+
+# Register Pointer Offset
+The off field indicates that each operand of type 0b01 (register pointer) has an 8 bit immediate.  This immediate is added to the value of the register before derefencing.
diff --git a/docs/instructions.md b/docs/instructions.md
@@ -8,8 +8,8 @@ description of the fox32 CPU and instruction encoding details, see [cpu.md](./cp
 
 ### ADD: add
 ### SUB: subtract
-### INC: increment (add 1)
-### DEC: decrement (subtract 1)
+### INC: increment (add 1/2/4/8)
+### DEC: decrement (subtract 1/2/4/8)
 ### CMP: compare
 ### AND: bitwise AND
 ### OR: bitwise OR