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Update in light of annotations refactor. #191

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Mar 1, 2018
Merged

Update in light of annotations refactor. #191

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7c7eaf1
Update in light of annotations refactor.
ucbjrl Mar 1, 2018
11bbb3c
Respond to review comments - simplify annotations.
ucbjrl Mar 1, 2018
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5 changes: 2 additions & 3 deletions src/main/scala/chisel3/iotesters/ChiselMain.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -112,11 +112,10 @@ object chiselMain {
(new firrtl.LowFirrtlEmitter).emit(firrtl.CircuitState(chirrtl, firrtl.ChirrtlForm), writer)
writer.close()
case _ if context.isGenVerilog =>
val annotations = firrtl.AnnotationMap(Seq(
firrtl.passes.memlib.InferReadWriteAnnotation(name)))
val annotations = Seq(firrtl.passes.memlib.InferReadWriteAnnotation)
val writer = new FileWriter(verilogFile)
val compileResult = (new firrtl.VerilogCompiler).compileAndEmit(
firrtl.CircuitState(chirrtl, firrtl.ChirrtlForm, Some(annotations)),
firrtl.CircuitState(chirrtl, firrtl.ChirrtlForm, annotations),
List(new firrtl.passes.memlib.InferReadWrite)
)
writer.write(compileResult.getEmittedCircuit.value)
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10 changes: 5 additions & 5 deletions src/main/scala/chisel3/iotesters/VCSBackend.scala
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Expand Up @@ -9,7 +9,7 @@ import chisel3.core.{ActualDirection, DataMirror}
import chisel3.{ChiselExecutionFailure, ChiselExecutionSuccess}
import firrtl.{ChirrtlForm, CircuitState}
import firrtl.annotations.CircuitName
import firrtl.transforms.{BlackBoxSourceHelper, BlackBoxTargetDir}
import firrtl.transforms.{BlackBoxSourceHelper, BlackBoxTargetDirAnno}

/**
* Copies the necessary header files used for verilator compilation to the specified destination folder
Expand Down Expand Up @@ -136,13 +136,13 @@ private[iotesters] object setupVCSBackend {
The following block adds an annotation that tells the black box helper where the
current build directory is, so that it can copy verilog resource files into the right place
*/
val annotationMap = firrtl.AnnotationMap(optionsManager.firrtlOptions.annotations ++ List(
val annotations = optionsManager.firrtlOptions.annotations ++ List(
firrtl.annotations.Annotation(
CircuitName(circuit.name),
classOf[BlackBoxSourceHelper],
BlackBoxTargetDir(optionsManager.targetDirName).serialize
BlackBoxTargetDirAnno(optionsManager.targetDirName).serialize
)
))
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Instead of using firrtl.annotations.Annotation(....) (which is deprecated), you can just use the BlackBoxTargetDirAnno, ie.

val annotations = optionsManager.firrtlOptions.annotations ++
  List(BlackBoxTargetDirAnno(optionsManager.targetDirName))

)

val transforms = optionsManager.firrtlOptions.customTransforms

Expand All @@ -151,7 +151,7 @@ private[iotesters] object setupVCSBackend {
val verilogWriter = new FileWriter(verilogFile)

val compileResult = (new firrtl.VerilogCompiler).compileAndEmit(
CircuitState(chirrtl, ChirrtlForm, Some(annotationMap)),
CircuitState(chirrtl, ChirrtlForm, annotations),
customTransforms = transforms
)
val compiledStuff = compileResult.getEmittedCircuit
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10 changes: 5 additions & 5 deletions src/main/scala/chisel3/iotesters/VerilatorBackend.scala
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Expand Up @@ -215,13 +215,13 @@ private[iotesters] object setupVerilatorBackend {
The following block adds an annotation that tells the black box helper where the
current build directory is, so that it can copy verilog resource files into the right place
*/
val annotationMap = firrtl.AnnotationMap(optionsManager.firrtlOptions.annotations ++ List(
val annotations = optionsManager.firrtlOptions.annotations ++ List(
firrtl.annotations.Annotation(
CircuitName(circuit.name),
classOf[BlackBoxSourceHelper],
BlackBoxTargetDir(optionsManager.targetDirName).serialize
BlackBoxTargetDirAnno(optionsManager.targetDirName).serialize
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Similar to the above

)
))
)

val transforms = optionsManager.firrtlOptions.customTransforms

Expand All @@ -232,7 +232,7 @@ private[iotesters] object setupVerilatorBackend {
val verilogWriter = new FileWriter(verilogFile)

val compileResult = (new firrtl.VerilogCompiler).compileAndEmit(
CircuitState(chirrtl, ChirrtlForm, Some(annotationMap)),
CircuitState(chirrtl, ChirrtlForm, annotations),
customTransforms = transforms
)
val compiledStuff = compileResult.getEmittedCircuit
Expand All @@ -245,7 +245,7 @@ private[iotesters] object setupVerilatorBackend {
val cppHarnessWriter = new FileWriter(cppHarnessFile)
val vcdFile = new File(dir, s"${circuit.name}.vcd")
val emittedStuff = VerilatorCppHarnessGenerator.codeGen(
dut, CircuitState(chirrtl, ChirrtlForm, Some(annotationMap)), vcdFile.toString
dut, CircuitState(chirrtl, ChirrtlForm, annotations), vcdFile.toString
)
cppHarnessWriter.append(emittedStuff)
cppHarnessWriter.close()
Expand Down