fuzhidai / CPU-Design-Based-on-RISC-V Public

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Development using Verilog programing language and Vivado IDE .

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Name		Name	Last commit message	Last commit date
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project_demo		project_demo
project_single_cycle		project_single_cycle
README.md		README.md

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注：

主文件为仿真文件 test_cpu_top.v ，运行该文件即可对整个 CPU 进行仿真；
可以直接将该项目导入 Vivado（不需要手动拷贝），具体方法自行上网了解；
inst_rom.v 和 data_mem.v 中配置的 inst_rom.data 和 data_rom.data 的文件目录需要按照本机进行更改；

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Development using Verilog programing language and Vivado IDE .

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