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Signed-off-by: Matthew Ballance <matt.ballance@gmail.com>
fvutils · Sep 6, 2024 · 80b594c · 80b594c
1 parent 80620cf
commit 80b594c
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Showing 3 changed files with 6 additions and 3 deletions.
diff --git a/src/pytest_fv/flow_sim.py b/src/pytest_fv/flow_sim.py
@@ -30,7 +30,7 @@ def __init__(self, dirconfig : DirConfig, sim_id = None):
         self.addSubPhase(PhasePrePost("generate"))
         self.addSubPhase(PhasePrePost("build"))
         self.addSubPhase(PhasePrePost("run"))
-        self.sim = HdlSim.create(dirconfig.builddir(), sim_id)
+        self.sim : HdlSim = HdlSim.create(dirconfig.builddir(), sim_id)
         self.addTool(self.sim, "sim")
         self.addTaskToPhase("build.main", self.sim.mkBuildTask())
 

diff --git a/src/pytest_fv/fv_config.py b/src/pytest_fv/fv_config.py
@@ -56,8 +56,8 @@ def getHdlSim(self):
 
         if "PYTEST_FV_HDLSIM" in os.environ.keys() and os.environ["PYTEST_FV_HDLSIM"] != "":
             return os.environ["PYTEST_FV_HDLSIM"]
-        elif "tool.hdlsim" in pytest_hdl.keys():
-            return pytest_hdl["tool.hdlsim"]
+        elif "hdlsim" in pytest_hdl.keys():
+            return pytest_hdl["hdlsim"]
         else:
             return FvConfig.DEFAULT_TOOL_HDLSIM
 

diff --git a/src/pytest_fv/tool/hdl/sim/sim_verilator.py b/src/pytest_fv/tool/hdl/sim/sim_verilator.py
@@ -81,6 +81,9 @@ async def build(self):
         if not os.path.isabs(logfile):
             logfile = os.path.join(self.builddir, logfile)
 
+        if not os.path.isdir(os.path.dirname(logfile)):
+            os.makedirs(os.path.dirname(logfile))
+
         print("cmd: %s" % str(cmd))
         with open(logfile, "w") as log:
             log.write("** Compile\n")