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[DSLX] Add advanced RunLengthEncoder
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This encoder is capable of ingesting multiple symbols
and produces multiple compressed pairs.
It should offer faster compression in exchange for area
used.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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mtdudek committed Jul 20, 2023
1 parent cc267b4 commit 7d9f08b
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209 changes: 209 additions & 0 deletions xls/modules/rle/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -106,6 +106,215 @@ xls_benchmark_ir(
},
)

xls_dslx_library(
name = "rle_enc_adv_reduce_stage_dslx",
srcs = [
"rle_enc_adv_reduce_stage.x",
],
deps = [
":rle_common_dslx"
],
)

xls_dslx_test(
name = "rle_enc_adv_reduce_stage_dslx_test",
dslx_test_args = {
"compare": "none",
},
library = "rle_enc_adv_reduce_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_reduce_stage_dslx_ir_test",
dslx_test_args = {
"compare": "interpreter",
},
library = "rle_enc_adv_reduce_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_reduce_stage_dslx_jit_test",
dslx_test_args = {
"compare": "jit",
},
library = "rle_enc_adv_reduce_stage_dslx",
)

xls_dslx_library(
name = "rle_enc_adv_realign_stage_dslx",
srcs = [
"rle_enc_adv_realign_stage.x",
],
deps = [
":rle_common_dslx"
],
)

xls_dslx_test(
name = "rle_enc_adv_realign_stage_dslx_test",
dslx_test_args = {
"compare": "none",
},
library = "rle_enc_adv_realign_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_realign_stage_dslx_ir_test",
dslx_test_args = {
"compare": "interpreter",
},
library = "rle_enc_adv_realign_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_realign_stage_dslx_jit_test",
dslx_test_args = {
"compare": "jit",
},
library = "rle_enc_adv_realign_stage_dslx",
)

xls_dslx_library(
name = "rle_enc_adv_core_dslx",
srcs = [
"rle_enc_adv_core.x",
],
deps = [
":rle_common_dslx"
],
)

xls_dslx_test(
name = "rle_enc_adv_core_dslx_test",
dslx_test_args = {
"compare": "none",
},
library = "rle_enc_adv_core_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_core_dslx_ir_test",
dslx_test_args = {
"compare": "interpreter",
},
library = "rle_enc_adv_core_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_core_dslx_jit_test",
dslx_test_args = {
"compare": "jit",
},
library = "rle_enc_adv_core_dslx",
)

xls_dslx_library(
name = "rle_enc_adv_adjust_width_stage_dslx",
srcs = [
"rle_enc_adv_adjust_width_stage.x",
],
deps = [
":rle_common_dslx"
],
)

xls_dslx_test(
name = "rle_enc_adv_adjust_width_stage_dslx_test",
dslx_test_args = {
"compare": "none",
},
library = "rle_enc_adv_adjust_width_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_adjust_width_stage_dslx_ir_test",
dslx_test_args = {
"compare": "interpreter",
},
library = "rle_enc_adv_adjust_width_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_adjust_width_stage_dslx_jit_test",
dslx_test_args = {
"compare": "jit",
},
library = "rle_enc_adv_adjust_width_stage_dslx",
)

xls_dslx_library(
name = "rle_enc_adv_dslx",
srcs = [
"rle_enc_adv.x",
],
deps = [
":rle_common_dslx",
":rle_enc_adv_reduce_stage_dslx",
":rle_enc_adv_realign_stage_dslx",
":rle_enc_adv_core_dslx",
":rle_enc_adv_adjust_width_stage_dslx",
],
)

xls_dslx_test(
name = "rle_enc_adv_dslx_test",
dslx_test_args = {
"compare": "none",
},
library = "rle_enc_adv_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_dslx_ir_test",
dslx_test_args = {
"compare": "interpreter",
},
library = "rle_enc_adv_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_dslx_jit_test",
dslx_test_args = {
"compare": "jit",
},
library = "rle_enc_adv_dslx",
)

xls_dslx_ir(
name = "rle_enc_adv_ir",
dslx_top = "RunLengthEncoder8_8_4_2",
library = "rle_enc_adv_dslx",
ir_file = "rle_enc_adv.ir",
)

xls_ir_opt_ir(
name = "rle_enc_adv_opt_ir",
src = "rle_enc_adv.ir",
top = "__xls_modules_rle_rle_enc_adv_core__RunLengthEncoder8_8_4_2__RunLengthEncoderAdvanced__RunLengthEncoderAdvancedCoreStage_0__8_4_8_next",
)

xls_ir_verilog(
name = "rle_enc_adv_verilog",
src = ":rle_enc_adv_opt_ir.opt.ir",
verilog_file = "rle_enc_adv.v",
codegen_args = {
"module_name": "rle_enc_adv",
"delay_model": "unit",
"pipeline_stages": "2",
"reset": "rst",
"use_system_verilog": "false",
},
)

xls_benchmark_ir(
name = "rle_enc_adv_ir_benchmark",
src = ":rle_enc_adv_opt_ir.opt.ir",
benchmark_ir_args = {
"pipeline_stages": "2",
"delay_model": "unit",
}
)

xls_dslx_library(
name = "rle_dec_dslx",
srcs = [
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