Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add drive strength register to LPC43XX SCU GPIO pin configuration #34

Conversation

antoinevg
Copy link
Member

@antoinevg antoinevg commented Oct 16, 2023

LPC43XX microcontrollers have 10 high-drive pins:

P1_17
P2_3
P2_4
P2_5
P8_0
P8_1
P8_2
PA_1
PA_2
PA_3

This PR extends the definition of the SCU pin configuration register block by adding the drive strength register at bits 9:8.

Reference:

UM10503 LPC43xx/LPC43Sxx ARM Cortex®-M4/M0 multi-core microcontroller User manual
Section 17.4.2 -- Pin configuration registers for high-drive pins.

@antoinevg antoinevg force-pushed the antoinevg/lpc43xx-gpio-drive-strength branch from 2bcb211 to 41102c1 Compare October 16, 2023 12:16
@antoinevg antoinevg force-pushed the antoinevg/lpc43xx-gpio-drive-strength branch from 41102c1 to fb5011a Compare October 16, 2023 12:17
Copy link
Member

@martinling martinling left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I've checked this against UM10503 and it all looks correct.

@antoinevg antoinevg merged commit 7871b38 into greatscottgadgets:master Oct 18, 2023
@antoinevg antoinevg deleted the antoinevg/lpc43xx-gpio-drive-strength branch October 19, 2023 13:10
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants