add AMX tile opcode and UOP mapping

add uop latency file for x86 spr

def/uop_latency_x86_spr.def

@@ -0,0 +1,80 @@
+/*
+Copyright (c) <2020>, <Georgia Institute of Technology> All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted 
+provided that the following conditions are met:
+
+Redistributions of source code must retain the above copyright notice, this list of conditions 
+and the following disclaimer.
+
+Redistributions in binary form must reproduce the above copyright notice, this list of 
+conditions and the following disclaimer in the documentation and/or other materials provided 
+with the distribution.
+
+Neither the name of the <Georgia Institue of Technology> nor the names of its contributors 
+may be used to endorse or promote products derived from this software without specific prior 
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR 
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 
+AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 
+OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
+POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+    /*
+     * The arguments to DEFUOP(opcode, latency) are as follows:
+     *  opcode  - opcode name
+     *  latency - opcode latency
+     */
+
+DEFUOP( UOP_INV,     1) 
+DEFUOP( UOP_NOP,     1)
+DEFUOP( UOP_CF,      1)
+DEFUOP( UOP_CMOV,    1)
+DEFUOP( UOP_LDA,     1)
+DEFUOP( UOP_IMEM,    1)
+DEFUOP( UOP_LD,      1)
+DEFUOP( UOP_ST,      1)
+DEFUOP( UOP_IADD,    1)
+DEFUOP( UOP_IMUL,    3)
+DEFUOP( UOP_IDIV,   26)
+DEFUOP( UOP_ICMP,    1)
+DEFUOP( UOP_LOGIC,   1)
+DEFUOP( UOP_SHIFT,   1)
+DEFUOP( UOP_BYTE,    1)
+DEFUOP( UOP_MM,      1)
+
+DEFUOP( UOP_VSTR,    3)
+DEFUOP( UOP_VADD,    1)
+DEFUOP( UOP_VFADD,   4)
+DEFUOP( UOP_AES,     4)
+DEFUOP( UOP_PCLMUL,  7)
+DEFUOP( UOP_X87,     3)
+DEFUOP( UOP_XSAVE, 112)
+DEFUOP( UOP_XSAVEOPT,84)
+
+DEFUOP( UOP_FMEM,    1)
+
+DEFUOP( UOP_LFENCE,     100)
+DEFUOP( UOP_FULL_FENCE, 100)
+DEFUOP( UOP_ACQ_FENCE,  100)
+DEFUOP( UOP_REL_FENCE,  100)
+
+DEFUOP( UOP_FCF,     1)
+DEFUOP( UOP_FCVT,    2)
+DEFUOP( UOP_FADD,    3)
+DEFUOP( UOP_FMUL,    5)
+DEFUOP( UOP_FDIV,   15)
+DEFUOP( UOP_FCMP,    2)
+DEFUOP( UOP_FBIT,    2)
+DEFUOP( UOP_FCMOV,   1)
+
+DEFUOP( UOP_SSE,     1)
+
+DEFUOP( UOP_AMX_COMPUTE_BF16,     100)

src/global_types.h

@@ -77,6 +77,7 @@ typedef enum uop_latency_map {  // enum for x86 latency maps - Michael
   LATENCY_SKYLAKE,
   LATENCY_SKYLAKE_X,
   LATENCY_COFFEE_LAKE,
+  LATENCY_SPR,
   NUM_LATENCY_MAPS
 } latency_map;
 

src/trace_read.h

@@ -286,6 +286,7 @@ typedef enum CPU_OPCODE_ENUM_ {
   XED_CATEGORY_3DNOW,
   XED_CATEGORY_ADOX_ADCX,
   XED_CATEGORY_AES,
+  XED_CATEGORY_AMX_TILE,
   XED_CATEGORY_AVX,
   XED_CATEGORY_AVX2,
   XED_CATEGORY_AVX2GATHER,
@@ -321,11 +322,15 @@ typedef enum CPU_OPCODE_ENUM_ {
   XED_CATEGORY_FMA4,
   XED_CATEGORY_GATHER,
   XED_CATEGORY_GFNI,
+  XED_CATEGORY_HRESET,
   XED_CATEGORY_IFMA,
   XED_CATEGORY_INTERRUPT,
   XED_CATEGORY_IO,
   XED_CATEGORY_IOSTRINGOP,
+  XED_CATEGORY_KEYLOCKER,
+  XED_CATEGORY_KEYLOCKER_WIDE,
   XED_CATEGORY_KMASK,
+  XED_CATEGORY_LEGACY,
   XED_CATEGORY_LOGICAL,
   XED_CATEGORY_LOGICAL_FP,
   XED_CATEGORY_LZCNT,
@@ -352,6 +357,7 @@ typedef enum CPU_OPCODE_ENUM_ {
   XED_CATEGORY_SCATTER,
   XED_CATEGORY_SEGOP,
   XED_CATEGORY_SEMAPHORE,
+  XED_CATEGORY_SERIALIZE,
   XED_CATEGORY_SETCC,
   XED_CATEGORY_SGX,
   XED_CATEGORY_SHA,
@@ -364,9 +370,11 @@ typedef enum CPU_OPCODE_ENUM_ {
   XED_CATEGORY_SYSRET,
   XED_CATEGORY_SYSTEM,
   XED_CATEGORY_TBM,
+  XED_CATEGORY_TSX_LDTRK,
   XED_CATEGORY_UNCOND_BR,
   XED_CATEGORY_VAES,
   XED_CATEGORY_VBMI2,
+  XED_CATEGORY_VEX,
   XED_CATEGORY_VFMA,
   XED_CATEGORY_VIA_PADLOCK,
   XED_CATEGORY_VPCLMULQDQ,

src/trace_read_cpu.cc

@@ -1249,6 +1249,8 @@ void cpu_decoder_c::init_pin_convert(void) {
   // init conversion based on knob value; this is only how they will be mapped and is independent of the UOP latency
   // values - Michael
   switch (lat_map) {
+    case LATENCY_SPR:
+      m_int_uop_table[XED_CATEGORY_AMX_TILE] = UOP_AMX_COMPUTE_BF16;
     case LATENCY_SKYLAKE:
     case LATENCY_COFFEE_LAKE:
       m_int_uop_table[XED_CATEGORY_INVALID] = UOP_INV;
@@ -2061,6 +2063,7 @@ const char *cpu_decoder_c::g_tr_opcode_names[MAX_TR_OPCODE_NAME] = {
   "3DNOW",
   "ADOX_ADCX",
   "AES",
+  "AMX_TILE",
   "AVX",
   "AVX2",
   "AVX2GATHER",
@@ -2096,11 +2099,15 @@ const char *cpu_decoder_c::g_tr_opcode_names[MAX_TR_OPCODE_NAME] = {
   "FMA4",
   "GATHER",
   "GFNI",
+  "HRESET",
   "IFMA",
   "INTERRUPT",
   "IO",
   "IOSTRINGOP",
+  "KEYLOCKER",
+  "KEYLOCKER_WIDE",
   "KMASK",
+  "LEGACY",
   "LOGICAL",
   "LOGICAL_FP",
   "LZCNT",
@@ -2127,6 +2134,7 @@ const char *cpu_decoder_c::g_tr_opcode_names[MAX_TR_OPCODE_NAME] = {
   "SCATTER",
   "SEGOP",
   "SEMAPHORE",
+  "SERIALIZE",
   "SETCC",
   "SGX",
   "SHA",
@@ -2139,9 +2147,11 @@ const char *cpu_decoder_c::g_tr_opcode_names[MAX_TR_OPCODE_NAME] = {
   "SYSRET",
   "SYSTEM",
   "TBM",
+  "TSX_LDTRK",
   "UNCOND_BR",
   "VAES",
   "VBMI2",
+  "VEX"
   "VFMA",
   "VIA_PADLOCK",
   "VPCLMULQDQ",

src/uop.h

@@ -52,6 +52,7 @@ typedef enum Iaq_Type_enum {
   mem_ALLOCQ,
   fp_ALLOCQ,
   simd_ALLOCQ,
+  tile_ALLOCQ,
   max_ALLOCQ
 } ALLOCQ_Type;
 
@@ -116,13 +117,16 @@ typedef enum Uop_Type_enum {
   // SIMD instructions for Intel GPU
   UOP_SIMD,
 
+  UOP_AMX_COMPUTE_BF16,
+
   // other instructions
   UOP_AES,  //!< AES enctyption
   UOP_PCLMUL,  //!< carryless multiplication
   UOP_X87,  //!< x87 ALU op
   UOP_XSAVE,  //!< XSAVE context switch
   UOP_XSAVEOPT,  //!< optimized XSAVE context switch
 
+
   // added on may-10-2012 for GPU instructions
   UOP_GPU_ABS,
   UOP_GPU_ABS64,