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Adjust cache controller for the changed SDRAM controller
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@gyurco
gyurco committed Feb 15, 2019
1 parent 9416cca commit a9ff6d7
Showing 1 changed file with 5 additions and 5 deletions.
10 changes: 5 additions & 5 deletions src/TwoWayCache.v
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Original file line number Diff line number Diff line change
Expand Up @@ -333,7 +333,7 @@ begin
begin
sdram_req<=1'b0;
data_to_cpu <= data_from_sdram;
cpu_ack<=1'b1; // Too soon?
//cpu_ack<=1'b1; // Too soon?

// write first word to Cache...
data_ports_w<={2'b11,data_from_sdram};
Expand All @@ -345,7 +345,7 @@ begin

FILL2:
begin
//cpu_ack<=cpu_req; // Maintain ack signal if necessary
cpu_ack<=1'b1; // Maintain ack signal if necessary
// write second word to Cache...
readword_burst<=1'b1;
readword<=readword+1'b1;
Expand All @@ -357,7 +357,7 @@ begin

FILL3:
begin
//cpu_ack<=cpu_req; // Maintain ack signal if necessary
//cpu_ack<=1'b1; // Maintain ack signal if necessary
// write third word to Cache...
readword_burst<=1'b1;
readword<=readword+1'b1;
Expand All @@ -382,8 +382,8 @@ begin
begin
//cpu_ack <= 1'b1;
readword<=cpu_addr[2:1];
// state<=WAITING;
state<=PAUSE1; // Allow one extra clock after clearing readword_burst
state<=WAITING;
// state<=PAUSE1; // Allow one extra clock after clearing readword_burst
end

default:
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