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Simplify compile process
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Changes to libcore means we need to do the compile in less passes.

Added the three new lang items, pulled support into zinc, app is still
the main entry point but it produces the .elf without a second call to
ld.

There has been a large size regression, the majority of it is from
libcore pulling in the string formatting functions for error handling.
I will submit a patch to provide a cfg flag for building libcore
with simpler errors.
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bharrisau committed May 26, 2014
1 parent 3098bdf commit a59ac75
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Showing 10 changed files with 67 additions and 47 deletions.
44 changes: 18 additions & 26 deletions Rakefile
Original file line number Diff line number Diff line change
Expand Up @@ -26,29 +26,25 @@ compile_rust :zinc_crate, {
recompile_on: [:triple, :platform, :features],
}

# zinc runtime support lib
compile_rust :zinc_support, {
source: 'lib/support.rs'.in_source,
produce: 'support.o'.in_intermediate,
llvm_pass: :inline,
lto: false,
recompile_on: :triple,
# dummy archives
compile_ar :dummy_morestack, {
produce: 'libmorestack.a'.in_intermediate,
}

# zinc isr crate
compile_rust :zinc_isr, {
source: 'hal/isr.rs'.in_source,
deps: :core_crate,
produce: 'isr.o'.in_intermediate,
recompile_on: [:triple, :features],
compile_ar :dummy_compiler_rt, {
produce: 'libcompiler-rt.a'.in_intermediate,
}

# zinc scheduler assembly
# TODO(farcaller): make platform-specific
if features.include?(:multitasking)
compile_c :zinc_isr_sched, {
compile_c :zinc_isr_sched_c, {
source: 'hal/cortex_m3/sched.S'.in_source,
produce: 'isr_sched.o'.in_intermediate,
produce: 'libisr_sched.o'.in_intermediate,
recompile_on: [:triple, :features],
}
compile_ar :zinc_isr_sched, {
source: 'libisr_sched.o'.in_intermediate,
produce: 'libisr_sched.a'.in_intermediate,
recompile_on: [:triple, :features],
}
end
Expand All @@ -65,22 +61,18 @@ app_tasks = Context.instance.applications.map do |a|
recompile_on: [:triple, :platform, :features],
}

compile_rust "app_#{a}".to_sym, {
compile_rust "app_#{a}_elf".to_sym, {
script: 'layout.ld'.in_platform,
source: 'lib/app.rs'.in_source,
deps: [
:core_crate,
:zinc_crate,
"app_#{a}_crate".to_sym,
],
produce: "app_#{a}.o".in_intermediate(a),
search_paths: a.in_intermediate,
}

link_binary "app_#{a}_elf".to_sym, {
script: 'layout.ld'.in_platform,
deps: ["app_#{a}".to_sym, :zinc_isr, :zinc_support] +
(features.include?(:multitasking) ? [:zinc_isr_sched] : []),
:dummy_morestack,
:dummy_compiler_rt,
] + (features.include?(:multitasking) ? [:zinc_isr_sched] : []),
produce: "app_#{a}.elf".in_build,
search_paths: [a.in_intermediate, "intermediate".in_build],
}

t_bin = make_binary "app_#{a}_bin".to_sym, {
Expand Down
8 changes: 0 additions & 8 deletions src/hal/isr.rs
Original file line number Diff line number Diff line change
Expand Up @@ -13,16 +13,8 @@
// See the License for the specific language governing permissions and
// limitations under the License.

//! This file is not part of zinc crate, it is linked separately, alongside the
//! ISRs for the platform.

#![feature(asm, globs)]
#![crate_id="isr"]
#![crate_type="staticlib"]
#![no_std]

extern crate core;

#[path="cortex_m3/isr.rs"] pub mod isr_cortex_m3;

#[cfg(mcu_lpc17xx)]
Expand Down
2 changes: 2 additions & 0 deletions src/hal/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,8 @@ and each such struct has a `setup()` method that configures the hardware

mod mem_init;

pub mod isr;

#[cfg(mcu_lpc17xx)] pub mod lpc17xx;
#[cfg(mcu_stm32f4)] pub mod stm32f4;

Expand Down
5 changes: 3 additions & 2 deletions src/hal/stack.rs
Original file line number Diff line number Diff line change
Expand Up @@ -16,13 +16,14 @@
//! Stack layout information.

extern {
static __STACK_BASE: u32;
// This is called an fn in ISR so needs to be an fn here.
fn __STACK_BASE();
static mut __STACK_LIMIT: u32;
}

/// Returns the address of main stack base (end of ram).
pub fn stack_base() -> u32 {
(&__STACK_BASE as *u32) as u32
(__STACK_BASE as *u32) as u32
}

/// Returns the current stack limit.
Expand Down
5 changes: 3 additions & 2 deletions src/lib/app.rs
Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,9 @@
//! for stack management, scheduler, ISRs and other symbols with global
//! visibility.

#![crate_type="staticlib"]
#![no_std]
#![no_start]
#![no_main]

extern crate core;
extern crate zinc;
Expand Down Expand Up @@ -48,6 +49,6 @@ pub extern fn __morestack() {
#[no_split_stack]
#[no_mangle]
#[cfg(cfg_multitasking)]
pub unsafe fn task_scheduler() {
pub unsafe extern fn task_scheduler() {
zinc::os::task::task_scheduler();
}
1 change: 1 addition & 0 deletions src/lib/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -19,3 +19,4 @@ pub mod strconv;
pub mod volatile_cell;
pub mod shared;
pub mod queue;
pub mod support;
19 changes: 12 additions & 7 deletions src/lib/support.rs
Original file line number Diff line number Diff line change
Expand Up @@ -13,17 +13,22 @@
// See the License for the specific language governing permissions and
// limitations under the License.

#![no_std]
#![crate_type="rlib"]
#![feature(asm)]

extern "rust-intrinsic" {
fn offset<T>(dst: *T, offset: int) -> *T;
}
use core::intrinsics::offset;

#[allow(non_camel_case_types)]
pub type c_int = i32;

#[lang = "stack_exhausted"]
extern fn stack_exhausted() { /* ... */ }

#[lang = "eh_personality"]
extern fn eh_personality() { /* ... */ }

#[lang = "begin_unwind"]
extern fn begin_unwind() {
abort()
}

#[no_mangle]
#[no_split_stack]
#[inline(never)]
Expand Down
1 change: 1 addition & 0 deletions src/os/syscall.rs
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ This module provides syscall interface that is implemented in assembly due to
current rust restrictions (see hal/cortex_m3/sched.S for actual implementation).
*/

#[link(name = "isr_sched")]
extern {
pub fn syscall(f: fn(u32), arg: u32);
}
4 changes: 4 additions & 0 deletions support/build/context.rb
Original file line number Diff line number Diff line change
Expand Up @@ -120,6 +120,10 @@ def initialize_environment!
"-L#{File.join(@env[:libs_path], @platform.arch.arch)}",
]

@env[:gccflags] = [
"-lgcc"
]

@env[:cflags] = [
'-mthumb',
"-mcpu=#{@platform.arch.cpu}",
Expand Down
25 changes: 23 additions & 2 deletions support/rake.rb
Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@ def compile_rust(n, h)
crate_type = h[:crate_type] ? "--crate-type #{h[:crate_type]}" : ""
ignore_warnings = h[:ignore_warnings] ? h[:ignore_warnings] : []
ignore_warnings = ignore_warnings.map { |w| "-A #{w}" }.join(' ')
script = h[:script]

declared_deps = h[:deps]
rust_src = h[:source]
Expand Down Expand Up @@ -65,7 +66,18 @@ def compile_rust(n, h)
'--emit asm'
else
''
end
end

mapfn = Context.instance.build_dir(File.basename(t.name, File.extname(t.name)) + '.map')

linker = case File.extname(t.name)
when '.elf'
"-C linker=#{:gcc.in_toolchain} " +
"-C link-args=\"-T #{script} -Wl,-Map=#{mapfn} " +
:gccflags.in_env.join(' ') + '"'
else
''
end

codegen = llvm_pass ? "-C passes=#{llvm_pass}" : ''

Expand All @@ -79,7 +91,7 @@ def compile_rust(n, h)

sh "#{:rustc.in_env} #{flags} " +
"#{do_lto ? '-Z lto' : ''} #{crate_type} #{emit} " +
"#{search_paths} #{codegen} " +
"#{search_paths} #{codegen} #{linker} " +
"#{outflags} #{ignore_warnings} #{rust_src}"
end
end
Expand Down Expand Up @@ -108,6 +120,15 @@ def compile_c(n, h)
end
end

def compile_ar(n, h)
h.resolve_deps!
Context.instance.rules[n] = h

Rake::FileTask.define_task(h[:produce] => [h[:source], h[:deps]].flatten.compact) do |t|
sh "#{:ar.in_toolchain} cr -o #{h[:produce]} #{h[:source]}"
end
end

def listing(n, h)
Rake::FileTask.define_task(h[:produce] => h[:source]) do |t|
sh "#{:objdump.in_toolchain} -D #{t.prerequisites.first} > #{t.name}"
Expand Down

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