Make it possible to switch off stackptr MPX optimization

hadeaninc · Oct 4, 2017 · 58b93a2 · 58b93a2
1 parent fc0667c
commit 58b93a2
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Showing 2 changed files with 75 additions and 26 deletions.
diff --git a/lib/Target/X86/MCTargetDesc/X86MCHadeanExpander.cpp b/lib/Target/X86/MCTargetDesc/X86MCHadeanExpander.cpp
@@ -25,6 +25,10 @@ cl::opt<bool> EnableMPX("hadean-mpx",
                         cl::desc("Hadean MPX assembly instrumentation"),
                         cl::init(false));
 
+cl::opt<bool> EnableMPXStackPtrOpt("hadean-mpx-stackptropt",
+                                   cl::desc("Hadean MPX stackptr optimization"),
+                                   cl::init(false));
+
 // To enable, pass '-mllvm --hadean-debug-cfi' to Clang.
 // TODO: This is enaled by default for now. Disable before putting into production!.
 cl::opt<bool> DebugCFI("hadean-debug-cfi",
@@ -311,7 +315,7 @@ bool HadeanExpander::HandleHadeanJump(MCStreamer &out, const PrefixInst &p_inst)
 }
 
 bool HadeanExpander::HandleMPX_StackPtrUpdate(MCStreamer &out, const PrefixInst &p_inst) {
-  if (!EnableMPX) {
+  if (!EnableMPX || !EnableMPXStackPtrOpt) {
     return false;
   }
 
@@ -369,8 +373,14 @@ bool HadeanExpander::HandleMPX_MemoryAccess(MCStreamer &out, const PrefixInst &p
   if (IsPush(p_inst.inst_, &size)) {
     boundsReg = kStackOpBoundsReg;
     memAddrLower.FromStackPtr(-size);
+    if (!EnableMPXStackPtrOpt) {
+      memAddrUpper.FromStackPtr(-1);
+    }
   } else if (IsPop(p_inst.inst_, &size)) {
     boundsReg = kStackOpBoundsReg;
+    if (!EnableMPXStackPtrOpt) {
+      memAddrLower.FromStackPtr(0); // TODO: optimize into BNDCL64rr
+    }
     memAddrUpper.FromStackPtr(size - 1);
   } else {
     boundsReg = desc.mayStore() ? kReadWriteBoundsReg : kReadOnlyBoundsReg;

diff --git a/test/MC/X86/Hadean/stack.s b/test/MC/X86/Hadean/stack.s
@@ -1,72 +1,111 @@
-// RUN: llvm-mc -hadean-mpx=true -assemble -triple=x86_64-hadean-linux -filetype obj < %s | llvm-objdump -d - | FileCheck %s
+// RUN: llvm-mc -hadean-mpx=true -hadean-mpx-stackptropt=false -assemble -triple=x86_64-hadean-linux -filetype obj < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK %s
+// RUN: llvm-mc -hadean-mpx=true -hadean-mpx-stackptropt=true -assemble -triple=x86_64-hadean-linux -filetype obj < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-OPT %s
 
 .text
 
 // ====== PUSH 16-BIT REGISTER ======
 
 pushw %dx
 
-// CHECK:      bndcl  -2(%rsp), %bnd3
-// CHECK-NEXT: pushw  %dx
+// CHECK:          bndcl  -2(%rsp), %bnd3
+// CHECK-NEXT:     bndcu  -1(%rsp), %bnd3
+// CHECK-NEXT:     pushw  %dx
+
+// CHECK-OPT:      bndcl  -2(%rsp), %bnd3
+// CHECK-OPT-NEXT: pushw  %dx
 
 // ====== PUSH 64-BIT REGISTER ======
 
 pushq %rdx
 
-// CHECK:      bndcl  -8(%rsp), %bnd3
-// CHECK-NEXT: pushq  %rdx
+// CHECK:          bndcl  -8(%rsp), %bnd3
+// CHECK-NEXT:     bndcu  -1(%rsp), %bnd3
+// CHECK-NEXT:     pushq  %rdx
+
+// CHECK-OPT:      bndcl  -8(%rsp), %bnd3
+// CHECK-OPT-NEXT: pushq  %rdx
 
 // ====== POP 16-BIT REGISTER ======
 
 popw %dx
 
-// CHECK:      bndcu  1(%rsp), %bnd3
-// CHECK-NEXT: popw   %dx
+// CHECK:          bndcl  (%rsp), %bnd3
+// CHECK-NEXT:     bndcu  1(%rsp), %bnd3
+// CHECK-NEXT:     popw  %dx
+
+// CHECK-OPT:      bndcu  1(%rsp), %bnd3
+// CHECK-OPT-NEXT: popw   %dx
 
 // ====== POP 64-BIT REGISTER ======
 
 popq %rdx
 
-// CHECK:      bndcu  7(%rsp), %bnd3
-// CHECK-NEXT: popq   %rdx
+// CHECK:          bndcl  (%rsp), %bnd3
+// CHECK-NEXT:     bndcu  7(%rsp), %bnd3
+// CHECK-NEXT:     popq  %rdx
+
+// CHECK-OPT:      bndcu  7(%rsp), %bnd3
+// CHECK-OPT-NEXT: popq   %rdx
 
 // ====== SET SPL REGISTER ======
 
 andb $42, %spl
 
-// CHECK:      andb $42, %spl
-// CHECK-NEXT: bndcl %rsp, %bnd3
-// CHECK-NEXT: bndcu -1(%rsp), %bnd3
+// CHECK:          andb $42, %spl
+// CHECK-NOT:      bndcl
+// CHECK-NOT:      bndcu
+
+// CHECK-OPT:      andb $42, %spl
+// CHECK-OPT-NEXT: bndcl %rsp, %bnd3
+// CHECK-OPT-NEXT: bndcu -1(%rsp), %bnd3
 
 // ====== SET SP REGISTER ======
 
 andw $1234, %sp
 
-// CHECK:      andw $1234, %sp
-// CHECK-NEXT: bndcl %rsp, %bnd3
-// CHECK-NEXT: bndcu -1(%rsp), %bnd3
+// CHECK:          andw $1234, %sp
+// CHECK-NOT:      bndcl
+// CHECK-NOT:      bndcu
+
+// CHECK-OPT:      andw $1234, %sp
+// CHECK-OPT-NEXT: bndcl %rsp, %bnd3
+// CHECK-OPT-NEXT: bndcu -1(%rsp), %bnd3
 
 // ====== SET ESP REGISTER ======
 
 andl $65000, %esp
 
-// CHECK:      andl $65000, %esp
-// CHECK-NEXT: bndcl %rsp, %bnd3
-// CHECK-NEXT: bndcu -1(%rsp), %bnd3
+// CHECK:          andl $65000, %esp
+// CHECK-NOT:      bndcl
+// CHECK-NOT:      bndcu
+
+// CHECK-OPT:      andl $65000, %esp
+// CHECK-OPT-NEXT: bndcl %rsp, %bnd3
+// CHECK-OPT-NEXT: bndcu -1(%rsp), %bnd3
 
 // ====== SET RSP REGISTER ======
 
 andq $65535, %rsp
 
-// CHECK:      andq $65535, %rsp
-// CHECK-NEXT: bndcl %rsp, %bnd3
-// CHECK-NEXT: bndcu -1(%rsp), %bnd3
+// CHECK:          andq $65535, %rsp
+// CHECK-NOT:      bndcl
+// CHECK-NOT:      bndcu
+
+// CHECK-OPT:      andq $65535, %rsp
+// CHECK-OPT-NEXT: bndcl %rsp, %bnd3
+// CHECK-OPT-NEXT: bndcu -1(%rsp), %bnd3
 
 // ====== POP INTO RSP REGISTER ======
 
 popq %rsp
 
-// CHECK:      bndcu 7(%rsp), %bnd3
-// CHECK-NEXT: popq %rsp
-// CHECK-NEXT: bndcl %rsp, %bnd3
-// CHECK-NEXT: bndcu -1(%rsp), %bnd3
+// CHECK:          bndcl  (%rsp), %bnd3
+// CHECK-NEXT:     bndcu  7(%rsp), %bnd3
+// CHECK:          popq %rsp
+// CHECK-NOT:      bndcl
+// CHECK-NOT:      bndcu
+
+// CHECK-OPT:      bndcu 7(%rsp), %bnd3
+// CHECK-OPT-NEXT: popq %rsp
+// CHECK-OPT-NEXT: bndcl %rsp, %bnd3
+// CHECK-OPT-NEXT: bndcu -1(%rsp), %bnd3