-
Notifications
You must be signed in to change notification settings - Fork 141
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Don't perform unaligned writes #133
Conversation
Must we always do this? It feel like this should be conditional on the platform. |
Yes, some platforms will let you get away with it (at a potential performance cost, especially if the kernel has to emulate it, such as on HP PA-RISC). GHC itself has a list of good and bad architectures (bewareLoadStoreAlignment in compiler/cmm/PprC.hs); I don't suppose there's an easy way to get that information? |
Indeed some platforms deal quite poorly with unaligned accesses; however, X86, which constitutes the majority of our users, is not one of these. AFAIK the penalty (assuming you don't cross a cache line) is only a cycle or two. However, this patch imposes an additional branch on all writes, aligned or otherwise. Mis-predicted branches are expensive yet sadly GHC doesn't currently give you the ability to ensure that it's predicted correctly. This is why I say we should make this conditional.
Hmm, sadly I don't there there is. However, maybe this is something that we want to expose; perhaps Naturally, this wouldn't help you today, but at least it's moving in the right direction. As for today, I think we'll just need to have some |
That might be sensible, but for now perhaps we could just run it through the preprocessor and use a bunch of |
Yep, I think that is the right answer for now. |
Updated to make use of the preprocessor. I'm not sure whether |
Indeed I'm a bit skeptical that |
I see, Regarding the CI failure, this is rather confusing and perhaps concerning. I can't reproduce them locally and presumably you can't either (right?). I'll also need to look into this. |
I can reproduce the issues, but they happen locally with master too. There are two problems:
|
Indeed, I have a commit fixing |
Alright, I believe the spurious failures should now be fixed. Sorry for the wait, @jrtc27. Do you think you could rebase this? |
All tests now passing :) |
Ping; is this blocked on the host/target macros issue, or mergeable as-is? |
We can merge as-is as far as I'm concerned. @dcoutts? |
Ping :) |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Ok. This is ok in that it works, but the extra with
allocation is going to be terrible for performance.
BTW, what about ARM platforms?
This is another example of why I want new ghc primops specifically for safe unaligned writes, since the compiler knows the platform and can probably do a better job at generating safe and reasonably good code for unaligned writes. For example some platforms have specific CPU instructions for unaligned reads & writes.
Old AArch32 (pre-v6) can do weird things on unaligned accesses (e.g. rotating the byte value by how many bytes you are off from the aligned-down address by), but I believe it works. In theory I think AArch64 can choose not to support unaligned accesses, but in practice I doubt that is enforced (and if the hardware doesn't support it, the kernel likely emulates it). Currently the unregisterised C backend assumes AArch32 and AArch64 cannot perform unaligned accesses, hence why I did not whitelist it here, but since there have been no bug reports about Cabal (which I saw reliably crashing due to this on SPARC with my experimental native code-gen) not working on these platforms, it's probably actually ok. I don't want to make that call and break it though as I'm no expert on Arm :) |
And yes, this isn't going to be great for performance, but unless you can think of a better solution (while GHC doesn't let you do a |
Ping; is there anything blocking this? Did you want me to whitelist AArch32 and/or AArch64? |
James Clarke <notifications@github.com> writes:
Ping; is there anything blocking this? Did you want me to whitelist AArch32 and/or AArch64?
Pinging @dcoutts.
|
yeah and it's wrong, I remember asking why this was made so but.. Anyways, for the ARM targets you can just check for the macro |
Updated; is that what you had in mind? |
Yeah, although |
Well, you'd hope so, but who knows; I just did that to be extra safe! I can simplify it if you want though. |
I'd say if something goes through the trouble of emulating |
So is everyone happy with this now? If so, could it be merged please? :) |
@jrtc27 one last thing... would you mind adding a Changelog entry to the 0.10.10 entry? then I'll happily merge this one. |
Some architectures, such as SPARC, trap on unaligned memory accesses, and poke makes no guarantees about its behaviour if the address is not sufficiently aligned. Therefore we should use a temporary buffer if asked to write to an unaligned address, unless we know for sure the architecture supports it without trapping.
Rebased with a changelog entry (sorry for the delay, I completely forgot about this). |
Ping |
Ping? Seems this got forgotten about by everyone involved. |
@hvr anything outstanding here? |
Ping |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
@jrtc27 could you please rebase? |
Closing in favour of #232 |
Some architectures, such as SPARC, trap on unaligned memory accesses, and poke makes no guarantees about its behaviour if the address is not sufficiently aligned. Therefore we should use a temporary buffer if asked to write to an unaligned address.