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A small RISC-V core in Python (and Verilog, soon)

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Name		Name	Last commit message	Last commit date
Latest commit History 47 Commits
docs		docs
riscv_core		riscv_core
tests		tests
.gitignore		.gitignore
README.md		README.md
requirements.txt		requirements.txt
ruff.toml		ruff.toml

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riscv-core

A small RISC-V core in Python (and Verilog, soon)

Prerequisite

RISC-V test suite: https://github.com/riscv-software-src/riscv-tests

Notes

RISC-V instruction decode

Run test

export PYTHONPATH=$(pwd)
pytest

TODO

Write a core in Python
Port over to Verilog

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A small RISC-V core in Python (and Verilog, soon)

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