Merge pull request #206 from mithro/asap7-improve

Adding all ASAP7 standard cell libraries.

WORKSPACE

@@ -93,12 +93,13 @@ llvm_toolchain(
 maybe(
     http_archive,
     name = "rules_7zip",
+    sha256 = "fd9e99f6ccb9e946755f9bc444abefbdd1eedb32c372c56dcacc7eb486aed178",
     strip_prefix = "rules_7zip-e00b15d3cb76b78ddc1c15e7426eb1d1b7ddaa3e",
     urls = ["https://github.com/zaucy/rules_7zip/archive/e00b15d3cb76b78ddc1c15e7426eb1d1b7ddaa3e.zip"],
-    sha256 = "fd9e99f6ccb9e946755f9bc444abefbdd1eedb32c372c56dcacc7eb486aed178",
 )
 
 load("@rules_7zip//:setup.bzl", "setup_7zip")
+
 setup_7zip()
 
 maybe(

dependency_support/com_icarus_iverilog/com_icarus_iverilog.bzl

@@ -22,7 +22,7 @@ def com_icarus_iverilog():
         http_archive,
         name = "com_icarus_iverilog",
         urls = [
-	    "https://github.com/steveicarus/iverilog/archive/v12_0.tar.gz",
+            "https://github.com/steveicarus/iverilog/archive/v12_0.tar.gz",
         ],
         strip_prefix = "iverilog-12_0",
         sha256 = "a68cb1ef7c017ef090ebedb2bc3e39ef90ecc70a3400afb4aa94303bc3beaa7d",

dependency_support/dependency_support.bzl

@@ -58,6 +58,8 @@ load("@rules_hdl//dependency_support/org_sourceware_libffi:org_sourceware_libffi
 load("@rules_hdl//dependency_support/org_swig:org_swig.bzl", "org_swig")
 load("@rules_hdl//dependency_support/org_theopenroadproject:org_theopenroadproject.bzl", "org_theopenroadproject")
 load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:org_theopenroadproject_asap7_pdk_r1p7.bzl", "org_theopenroadproject_asap7_pdk_r1p7")
+load("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc6t_26:org_theopenroadproject_asap7sc6t_26.bzl", "org_theopenroadproject_asap7sc6t_26")
+load("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc7p5t_27:org_theopenroadproject_asap7sc7p5t_27.bzl", "org_theopenroadproject_asap7sc7p5t_27")
 load("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc7p5t_28:org_theopenroadproject_asap7sc7p5t_28.bzl", "org_theopenroadproject_asap7sc7p5t_28")
 load("@rules_hdl//dependency_support/pybind11:pybind11.bzl", "pybind11")
 load("@rules_hdl//dependency_support/tk_tcl:tk_tcl.bzl", "tk_tcl")
@@ -105,6 +107,8 @@ def dependency_support():
     org_swig()
     org_theopenroadproject()
     org_theopenroadproject_asap7_pdk_r1p7()
+    org_theopenroadproject_asap7sc6t_26()
+    org_theopenroadproject_asap7sc7p5t_27()
     org_theopenroadproject_asap7sc7p5t_28()
     pybind11()
     tk_tcl()

dependency_support/org_theopenroadproject_asap7_pdk_r1p7/BUILD

@@ -15,6 +15,7 @@
 exports_files([
     "tracks.tcl",
     "rc_script.tcl",
-    "pdn_config.pdn",
+    "pdn_config_1x.pdn",  # FIXME: Where did this come from?
+    "pdn_config_4x.pdn",  # FIXME: Where did this come from?
     "asap7.lyt",  # Imported from OpenROAD-flow-scripts on 24.07.2023 at 6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8 from: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8/flow/platforms/asap7/KLayout/asap7.lyt
 ])

dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl

@@ -3,11 +3,163 @@
 load("@rules_hdl//pdk:build_defs.bzl", "CornerInfo", "StandardCellInfo")
 load("@rules_hdl//pdk:open_road_configuration.bzl", "OpenRoadPdkInfo")
 
+def asap7_srams_files(name = None, rev = None, tracks = None, has_gds = True):
+    """Generate ASAP7 sram's filegroup targets (asap7-cells-XXX).
+
+    Args:
+      name: Macro instance name.
+      rev: ASAP7 revision ("26" / "27" / "28").
+      tracks: Number of tracks ("7p5t", "6t").
+      has_gds: SRAM have GDS layouts.
+    """
+
+    if rev not in ["26", "27", "28"]:
+        fail("Invalid rev {}".format(repr(rev)))
+    if tracks not in ["7p5t", "6t"]:
+        fail("Invalid rev {}".format(repr(tracks)))
+
+    args = {
+        "rev": str(rev),
+        "tracks": str(tracks),
+    }
+
+    # Layouts for GDS generation
+    # ------------------------------------------------------------------------
+    if has_gds:
+        native.filegroup(
+            name = "asap7-srams-sc{tracks}_rev{rev}-gds".format(**args),
+            srcs = native.glob(["GDS/asap7sc{tracks}_{rev}*_SRAM_*.gds".format(**args)]),
+        )
+
+    # Timing information (in compressed Liberty format) for synthesis and static
+    # timing analysis (STA).
+    # ------------------------------------------------------------------------
+    native.filegroup(
+        name = "asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args),
+        srcs = native.glob(["LIB/CCS/*SRAM*.lib.7z".format(**args)]),
+    )
+
+    # Verilog models for digital simulation and logical equivalence
+    # ------------------------------------------------------------------------
+    native.filegroup(
+        name = "asap7-srams-sc{tracks}_rev{rev}-v".format(**args),
+        srcs = native.glob(["Verilog/asap7sc{tracks}_*_SRAM_*.v".format(**args)]),
+    )
+
+    # CDL models for LVS checking
+    # ------------------------------------------------------------------------
+    native.filegroup(
+        name = "asap7-srams-sc{tracks}_rev{rev}-lvs".format(**args),
+        srcs = native.glob(["CDL/LVS/asap7sc{tracks}_{rev}_*SRAM*.cdl".format(**args)]),
+    )
+
+    # CDL models for Spice simulation
+    # ------------------------------------------------------------------------
+    native.filegroup(
+        name = "asap7-srams-sc{tracks}_rev{rev}-spice".format(**args),
+        srcs = native.glob(["CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_*SRAM*.sp".format(**args)]),
+    )
+
+    # Place and route
+    # ------------------------------------------------------------------------
+    native.filegroup(
+        name = "asap7-srams-sc{tracks}_rev{rev}-lef".format(**args),
+        srcs = native.glob(["LEF/asap7sc{tracks}_{rev}*_SRAM_*.lef".format(**args)]),
+    )
+
+def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds = True):
+    """Generate ASAP7 cell's filegroup targets (asap7-cells-XXX).
+
+    Args:
+      name: Macro instance name.
+      rev: ASAP7 revision ("26" / "27" / "28").
+      tracks: Number of tracks ("7p5t", "6t").
+      vt: VT type ("rvt", "lvt", "slvt").
+      has_gds: Cells have GDS layouts.
+    """
+
+    if rev not in ["26", "27", "28"]:
+        fail("Invalid rev {}".format(repr(rev)))
+    if tracks not in ["7p5t", "6t"]:
+        fail("Invalid tracks {}".format(repr(tracks)))
+    if vt not in ["lvt", "rvt", "slvt"]:
+        fail("Invalid vt {}".format(repr(vt)))
+
+    args = {
+        "rev": rev,
+        "tracks": tracks,
+        "vt_long": vt,
+        "vt_upper": vt.upper(),
+        "vt_short": {"rvt": "R", "lvt": "L", "slvt": "SL"}[vt],
+    }
+
+    # Layouts for GDS generation
+    # ------------------------------------------------------------------------
+    if has_gds:
+        native.filegroup(
+            name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args),
+            srcs = native.glob(["GDS/asap7sc{tracks}_{rev}_{vt_short}*.gds".format(**args)]),
+        )
+
+    # Timing information (in compressed Liberty format) for synthesis and static
+    # timing analysis (STA).
+    # ------------------------------------------------------------------------
+    native.filegroup(
+        name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args),
+        srcs = native.glob(["LIB/CCS/*_{vt_upper}_*.lib.7z".format(**args)]),
+    )
+
+    # Verilog models for digital simulation and logical equivalence
+    # ------------------------------------------------------------------------
+    native.filegroup(
+        name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-v".format(**args),
+        srcs = native.glob(["Verilog/asap7sc{tracks}_*_{vt_upper}_*.v".format(**args)]),
+    )
+
+    # CDL models for LVS checking
+    # ------------------------------------------------------------------------
+    native.filegroup(
+        name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lvs".format(**args),
+        srcs = native.glob(["CDL/LVS/asap7sc{tracks}_{rev}_{vt_short}.cdl".format(**args)]),
+    )
+
+    # CDL models for Spice simulation
+    # ------------------------------------------------------------------------
+    native.filegroup(
+        name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-spice".format(**args),
+        srcs = native.glob(["CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_{vt_short}.sp".format(**args)]),
+    )
+
+    # Place and route
+    # ------------------------------------------------------------------------
+    native.filegroup(
+        name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args),
+        srcs = native.glob(["LEF/asap7sc{tracks}_{rev}_{vt_short}_1x*.lef".format(**args)]),
+    )
+
+    # Library configuration
+    # ------------------------------------------------------------------------
+    asap7_cell_library(
+        name = "asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args),
+        srcs = [
+            ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args),
+            #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args),
+        ],
+        cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args),
+        platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args),
+        default_corner_delay_model = "ccs",
+        default_corner_swing = "SS",
+        openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args),
+        tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args),
+        visibility = [
+            "//visibility:public",
+        ],
+    )
+
 def _asap7_cell_library_impl(ctx):
     liberty_files = [file for file in ctx.files.srcs if file.extension == "7z"]
     liberty_files = [file for file in liberty_files if "_{}_".format(ctx.attr.default_corner_delay_model) in file.basename]
     liberty_files = [file for file in liberty_files if "SRAM" not in file.basename]
-    liberty_files = [file for file in liberty_files if ctx.attr.cell_type in file.basename]
 
     uncompressed_files = []
     for file in liberty_files:
@@ -72,11 +224,10 @@ asap7_cell_library = rule(
         "tech_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The tech lef file for these standard cells"),
         "default_corner_swing": attr.string(mandatory = True, values = ["SS", "FF", "TT"]),
         "default_corner_delay_model": attr.string(mandatory = True, values = ["ccs", "ccsn", "ccsa"]),
-        "cell_type": attr.string(mandatory = True, values = ["RVT", "LVT", "SLVT"]),
         #TODO(b/212480812): Support multiple VTs in a single design.
         "openroad_configuration": attr.label(providers = [OpenRoadPdkInfo]),
         "cell_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The lef file for the standard cells"),
-        "platform_gds": attr.label(allow_single_file = True, mandatory = True, doc = "Platform GDS files"),
+        "platform_gds": attr.label(allow_single_file = True, mandatory = False, doc = "Platform GDS files"),
         "_combine_liberty": attr.label(
             default = Label("@rules_hdl//pdk/liberty:combine_liberty"),
             executable = True,

dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py

@@ -0,0 +1,91 @@
+#!/usr/bin/env python3
+# Copyright 2023 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import pathlib
+
+__path__ = pathlib.Path(__file__).resolve()
+__dir__ = __path__.parent
+
+license_header = []
+for l in open(__path__).readlines()[1:]:
+    if not l.startswith('#'):
+        break
+    license_header.append(l)
+
+header = []
+header.extend(license_header)
+header.append('\n')
+header.append('# DO NOT EDIT - This file is generated by `build-BUILD.py` script!\n')
+header.append('\n')
+header.append('''\
+"""
+ASAP7 -- Arizona State University 7nm "predictive" PDK
+
+The PDK has RVT, LVT and SLVT based transistors.
+
+The ASAP7 PDK currently provides 3 standard cell libraries;
+ * Two revisions (rev 27 and rev 28) of a 7.5 track library
+ * One revision (rev 26) of a 6 track library
+
+These libraries are mapped to each of the transistor types;
+ * RVT -> R
+ * LVT -> L
+ * SLVT -> SL
+
+It also provides "4x scaled" versions of these libraries. These versions reuse
+the same timing information but have their sizes scaled up.
+
+The libraries provide 3 corners,
+ * FF - fast
+ * TT - typical
+ * SS - slow
+
+By default if not otherwise explicitly specified the default selection will be
+the 7.5 track library using RVT transistors and slow corner.
+"""
+
+load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration")
+load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library")
+load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cells_files")
+load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_srams_files")
+
+''')
+
+for scdir in list(sorted(__dir__.parent.glob('org_theopenroadproject_asap7sc*'))):
+    print('Processing ', scdir)
+    output = []
+    output.extend(header)
+
+    common_file = scdir / 'common.bzl'
+    assert common_file.exists(), common_file
+
+    input_files = [common_file] + list(scdir.glob('cells-*.bzl'))
+    input_files.sort()
+    for input_file in input_files:
+        output.append(f"""
+# From {scdir.name}/{input_file.name}
+""")
+        print('Reading', input_file)
+        with open(input_file) as f:
+            lines = f.readlines()
+            while lines.pop(0) in license_header:
+                continue
+            output.extend(lines)
+
+    output_file = scdir / 'bundled.BUILD.bazel'
+    print('Writing', output_file)
+    with open(output_file, 'w') as f:
+        for l in output:
+            f.write(l)

dependency_support/org_theopenroadproject_asap7_pdk_r1p7/bundled.BUILD.bazel

@@ -12,5 +12,3 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-"""Arizona State University 7nm PDK"""
-

dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7_pdk_r1p7.bzl

@@ -22,7 +22,7 @@ def org_theopenroadproject_asap7_pdk_r1p7():
         http_archive,
         name = "org_theopenroadproject_asap7_pdk_r1p7",
         urls = [
-            "https://github.com/The-OpenROAD-Project/asap7_pdk_r1p7/archive/1ff7649bbf423207f6f70293dc1cf630cd477365.tar.gz"
+            "https://github.com/The-OpenROAD-Project/asap7_pdk_r1p7/archive/1ff7649bbf423207f6f70293dc1cf630cd477365.tar.gz",
         ],
         strip_prefix = "asap7_pdk_r1p7-1ff7649bbf423207f6f70293dc1cf630cd477365",
         sha256 = "b5847f93e55debb49d03ec581e22eb301109ff90c9ad19d35ae1223c70250391",

dependency_support/org_theopenroadproject_asap7_pdk_r1p7/pdn_config_4x.pdn

@@ -0,0 +1,44 @@
+# Floorplan information - core boundary coordinates, std. cell row height,
+
+set ::halo 2
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
+
+# Power nets
+set ::power_nets "VDD"
+set ::ground_nets "VSS"
+
+####################################
+# global connections
+####################################
+add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
+add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$}
+add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$}
+add_global_connection -defer_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
+add_global_connection -defer_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$}
+global_connect
+####################################
+# voltage domains
+####################################
+set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
+####################################
+# standard cell grid
+####################################
+# ASAP7 in its default configuration is multipled by
+# 4x looking to fix this upstream.
+set multipler 4.0
+
+define_pdn_grid -name {top} -voltage_domains {CORE}
+add_pdn_stripe -grid {top} -layer {M1} -width {0.072} -pitch {2.16} -offset {0} -followpins
+add_pdn_stripe -grid {top} -layer {M2} -width {0.072} -pitch {2.16} -offset {0} -followpins
+add_pdn_stripe -grid {top} -layer {M5} -width {0.48} -spacing {0.288} -pitch {47.52} -offset {1.188}
+add_pdn_stripe -grid {top} -layer {M6} -width {1.1520} -spacing {0.384} -pitch {48} -offset {2.556}
+add_pdn_connect -grid {top} -layers {M1 M2}
+add_pdn_connect -grid {top} -layers {M2 M5}
+add_pdn_connect -grid {top} -layers {M5 M6}
+
+pdn::allow_repair_channels true

dependency_support/org_theopenroadproject_asap7sc6t_26/BUILD

@@ -0,0 +1,13 @@
+# Copyright 2022 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.