VHDL highlights.scm improvement

[Chris44442]

Hi, the highlighting for the VHDL language is very basic and is missing a lot of features. My changes fixes that. I'd like to think these are sane defaults and also minimalist.

@teburd

[teburd]

Ultimately good vhdl highlighting needs more context than what I think a tree sitter grammar can provide. Frankly its a language that could do well with an lsp highlighter imo after looking at this as it requires a deeper understanding of the context than simply grammatical rules around whats valid/invalid. I found no one in the helix matrix chat could help me improve the queries/highlights :( If you manage to do better, by all means do so!

Many things in vhdl are modules but are effectively so common as to be builtins. Treating them as builtins though is wrong.

I compared your changes to helix master, to emacs vhdl major mode. Emacs major mode is still significantly better at highlighting but I think this PR does make things look a bit nicer.

Missing from helix that I can see in comparison to emacs vhdl major mode...

• bit value highlights ('0', '1', 'Z', etc)
• builtin function highlights
• function highlights
• differentiable process and entity name highlights

Emacs vhdl major mode left side, helix with your changes right side show neorv32_fifo.vhd (stnolting's sweet open source riscv core)

[Chris44442]

My guess is that we will not have an LSP based VHDL highlighting in the near future. For now we will have to use tree-sitter-vhdl.

There are of course a few problems. The main one being that the maintainer has disappeared years ago. Second the "function_call" problem, which partly the VHDL language is to blame, and what you said. The words I filed under function.builtin are a workaround, because I can't fix the root problem in the parser. Thirdly there is the error highlighting, which should not be done by a tree-sitter parser as most agree. And lastly there are some problems in the code and also with the "offical" highlighting.scm file. This is why nvim-treesitter has rejected tree-sitter-vhdl so far (a parser rewrite is being discussed right now). Either way: Helix uses it.

In your screenshot you are using the default theme with no customization. Tbh I am not sure why so many constructs highlighting are missing from the themes by default. Anyway you need to set operator, keyword.operator, number, character, string and maybe one or two more in the theme settings. Like so:

character = { fg = "light-green" }
number = { fg = "red" }
operator = { fg = "green" }

I tried to mimic the Verilog highlights.scm from the official tree-sitter repo. Due to the issues that I mentioned above there was only so much I could do. Not all of the functions are highlighted, with no way of fixing it in the .scm file sadly. This is obviously subjective but imho the highlighting looks a lot better with the PR than without it. With my theme settings this is the comparison between the current highlights.scm (top) and my PR (bottom). Imho there is not too much difference from my PR to the Emacs screenshot.

[teburd]

Looks nice, now why is the default theme so meh then, send another PR :)

[Chris44442]

Looks nice, now why is the default theme so meh then, send another PR :)

Mh yeah I am a bit hesitant because it literally concerns all themes. At first I thought it was a deliberate choice.

[Chris44442]

@archseer

I have addressed all the requested changes. Can we merge?