Co Pro RISC-V: Fix CSR immediate disassembly bug

Change-Id: I279eb103d8692f1af6cfc07d5351fbf5238c1ca8
hoglet67 · Sep 19, 2023 · 4094004 · 4094004
1 parent 78e06a6
commit 4094004
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/src/riscv/riscv_disas.c b/src/riscv/riscv_disas.c
@@ -292,9 +292,6 @@ const char *op2(int fmt, const union encoding *e, uint32_t pc) {
       return reg_name[e->rs2];
    case I:
       i = e->i.i11_0;
-      if (i & 0x800) {
-         i -= 0x1000;
-      }
       if (e->opcode == 0x73 && (e->funct3 & 3)) {
          // CSR
          switch (i) {
@@ -323,6 +320,9 @@ const char *op2(int fmt, const union encoding *e, uint32_t pc) {
          }
          sprintf(imm, "0x%03x", i);
       } else {
+         if (i & 0x800) {
+            i -= 0x1000;
+         }
          sprintf(imm, "%d", i);
       }
       return imm;