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feat: add sent reason for late arriving spans #936
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kentquirk
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I just want to note that we went over this on a call and the benchmarks showed that this cache design is extremely fast, since it's lockless on read. We also tested for race conditions in parallel operation.
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Which problem is this PR solving?
Short description of the changes
This PR adds a new cache for send_reasons that Refinery produces for a given configuration.
The new cache acts as a mapping between the string representation of send reason and a uint.
The cache is used to reduce the memory footprint of the trace cache.
I made the design based on the assumption that the send reason has a low cardinality for a given configuration.
We decided not to clear out the cache on config reload so that we can avoid needing a lock on read operation.
fix #835