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irjit: Fix unordered float compares #16305

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merged 2 commits into from
Oct 31, 2022
Merged

irjit: Fix unordered float compares #16305

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56ff555
irjit: Fix unordered float compares.
unknownbrackets Oct 31, 2022
2da1bf7
interp: Correct dprefix accuracy for vrot.
unknownbrackets Oct 31, 2022
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4 changes: 2 additions & 2 deletions Core/MIPS/IR/IRCompALU.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -118,7 +118,7 @@ void IRFrontend::Comp_RType3(MIPSOpcode op) {
MIPSGPReg rd = _RD;

// noop, won't write to ZERO.
if (rd == 0)
if (rd == MIPS_REG_ZERO)
return;

switch (op & 63) {
Expand Down Expand Up @@ -298,7 +298,7 @@ void IRFrontend::Comp_Allegrex2(MIPSOpcode op) {
MIPSGPReg rd = _RD;

// Don't change $zr.
if (rd == 0)
if (rd == MIPS_REG_ZERO)
return;

switch (op & 0x3ff) {
Expand Down
2 changes: 1 addition & 1 deletion Core/MIPS/IR/IRCompFPU.cpp
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Expand Up @@ -118,7 +118,7 @@ void IRFrontend::Comp_FPUComp(MIPSOpcode op) {
break;
case 3: // ueq, ngl (equal, unordered)
mode = IRFpCompareMode::EqualUnordered;
return;
break;
case 4: // olt, lt (less than, ordered)
mode = IRFpCompareMode::LessOrdered;
break;
Expand Down
1 change: 1 addition & 0 deletions Core/MIPS/IR/IRCompVFPU.cpp
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Expand Up @@ -464,6 +464,7 @@ namespace MIPSComp {
init = Vec4Init::AllONE;
break;
default:
INVALIDOP;
return;
}
ir.Write(IROp::Vec4Init, vec[0], (int)init);
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12 changes: 9 additions & 3 deletions Core/MIPS/IR/IRInterpreter.cpp
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Expand Up @@ -881,17 +881,23 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
break;
}
case IRFpCompareMode::EqualOrdered:
case IRFpCompareMode::EqualUnordered:
mips->fpcond = mips->f[inst->src1] == mips->f[inst->src2];
break;
case IRFpCompareMode::EqualUnordered:
mips->fpcond = mips->f[inst->src1] == mips->f[inst->src2] || my_isnan(mips->f[inst->src1]) || my_isnan(mips->f[inst->src2]);
break;
case IRFpCompareMode::LessEqualOrdered:
case IRFpCompareMode::LessEqualUnordered:
mips->fpcond = mips->f[inst->src1] <= mips->f[inst->src2];
break;
case IRFpCompareMode::LessEqualUnordered:
mips->fpcond = !(mips->f[inst->src1] > mips->f[inst->src2]);
break;
case IRFpCompareMode::LessOrdered:
case IRFpCompareMode::LessUnordered:
mips->fpcond = mips->f[inst->src1] < mips->f[inst->src2];
break;
case IRFpCompareMode::LessUnordered:
mips->fpcond = !(mips->f[inst->src1] >= mips->f[inst->src2]);
break;
}
break;

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5 changes: 3 additions & 2 deletions Core/MIPS/MIPSIntVFPU.cpp
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Expand Up @@ -1629,8 +1629,9 @@ namespace MIPSInt
d[cosineLane] = cosine;
}

// D prefix works, just not for x.
currentMIPS->vfpuCtrl[VFPU_CTRL_DPREFIX] &= 0xFFEFC;
// D prefix works, just not for the cosine lane.
uint32_t dprefixRemove = (3 << cosineLane) | (1 << (8 + cosineLane));
currentMIPS->vfpuCtrl[VFPU_CTRL_DPREFIX] &= 0xFFFFF ^ dprefixRemove;
ApplyPrefixD(d, sz);
WriteVector(d, sz, vd);
PC += 4;
Expand Down