Tiny RISCV emulator written in C. Started off as a python implementation following geohot's twitchcore and ultimately evolved into a more in-depth C/C++ implementation.
Status: passes all tests!
You first need to build the tests for RISC-V emulators. This particular repo only implements rv32ui - RV32, user level, integer only. The test suite only runs the p environment which disables the use of virtual memory and only allows for one core.
Clone and build the submodules of this repository:
git submodule update --init --recursive
cd riscv-tests
./configure
make -jNow you should be able to see the RISCV tests listed in the directory
riscv-tests/isa/
If you got an error during the make stage, make sure you have the RISCV toolkit installed on your operating system.
Installation for RISCVem is simple:
mkdir build
cd build
cmake ..
makeIf you wish to run an automated test of the emulator, run the included test binary which performs all tests for RV32UI single mode, raw memory, privileged mode of RISCV:
./rv32ui_testsIf you have your own ELF binary, then run:
./riscvem -f <path to your ELF> -v 1Note that by default, verbosity level is set to 0. So you will only know if your code ran through the return value of the program. There are three levels of verbosity you can use. The highest level: 2 will print a dump of the 8 words of memory near the program counter address + values of all registers at each step of execution.