Gtwrapper #5
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Gtwrapper #5
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Changes: - z7_gtx_evr was generated using the wizard using the parameterization values that were used in MRF's code. The link speed has been modified to fit the ESS deployment. - trasceiver_dc_k7 has been slightly modified to instantiate the new IP and perform the modifications based in the new interface of the IP. [ICSHWI-4769]
Changes: - Some code cleaning - Moved upwards the clock buffer instantiation - Changed the DC module for the new gtx wrapper - Moved the component declaration to the package [ICSHWI-4769]
Changes: - Renamed transceiver_dc_k7.vhd -> transceiver_dc_z7.vhd - Inlcuded transceiver .xci IP as source in ess-openevr IP - Updates to component.xml to reflect all of above [ICSHWI-4769]
[ICSHWI-4609]
Changes: - New package to include signal/constant definitions for the GT wrapper - Packages have been moved to an isolated folder
Gtwrapper
With the IP based structure, compilation using Make is no longer needed. Documentation generation remains.
This header should be used as template to fix the resting files. Changes: - Division lines break the block, leading to undesired result in the generated doc. - Reordered tokens order to improve the final result.
Changes: - Initial register bank added to IP core (AXI4-Lite) - Base address: 0x43c00000 - Master reset register is located at the base address (offset 0x0) [ICSHWI-4769]
Changes: - A reset module has been added to generate a reset pulse compliant with the reset signal restrictions of the GT. - Cleaned the instantiation of the GT wrapper. - Interface change to include the ctrl&reset records. - More cleanup of the old stuff. [ICSHWI-4769]
Interfaces for all the modules in the hierarchy have been modified to include the records. [ICSHWI-4769]
Changed imports to match the new lib name. [ICSHWI-4605]
Changes: - Updated some component interfaces - Moved component definitions to the package file
Changes: - Connect reset signals from register bank to transceiver - Tidy up IP block mask
Changes: - RxDataValid: default high value. - RXUserRdy: tied to vcc. [ICSHWI-4822]
Changes: - Added an input port for a free running debug clock (usefull for sampling rate of the ILA) - Latched resets coming from the AXI clock domain. - Removed old code. [ICSHWI-4822]
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Feel free to squash everything in a commit, it's not a big deal to have these as sepparate commits.