[GSoC] Common Verilog Generation API and Implementation in `temp-sense-gen` #212

harshkhandeparkar · 2023-05-31T10:33:10Z

Part of #211.

Changes

Added a common Python module in openfasoc/generators/common.
Added a common function for Verilog generation using Mako templates.
Added Mako as a dependency in requirements.txt.
Used the new Verilog generation function in the temp-sense-gen generator.
Converted temp-sense-gen Verilog source code to Mako templates.
Added tests for the new Python module in tests/ which are run by the pytest module in the CI (test_code.yml workflow)
Updated the documentation in docs/ to reflect the changes in filename and the new Mako-based templating format.

Results

The changed temp-sense-gen generator flow runs without any issues.

* uncommented code which inserts the designName in config.mk * removed code which inserts the designName parameter in Verilog

* removed previous code used to generate output Verilog * removed previous code used to copy generated Verilog

* removed code which replaces `.template` in source Verilog filenames because it seemed unncessary

because it's output filename is the same as the input filename

* added docstring to the __init__.py file * added docstrings to the functions defined in verilog_generation module

* added commonly used Verilog functions as defs in the Mako template * updated the source verilog code to use the new defs * added a TODO: comment to improve this way of importing defs in the future

msaligane · 2023-05-31T13:13:58Z

@alibillalhammoud can you review too?

* uncommented code for generating `blocks/sky130hd/tempsenseInst_custom_net.txt` and `blocks/sky130hd/tempsenseInst_domain_insts.txt` files * updated the source file path to reflect the changes in Verilog generation

alibillalhammoud

Looks good

* renamed all functions beginning with double _ to single _ to make them accessible using import <module_name>

saicharan0112 · 2023-06-05T15:37:16Z

Apologies for the late response, I didn't knew that I was requested a review on this. Let me review this by today.

* Added unit tests using pytest in test/ directory * Used part of temp-sense-gen Verilog for unit tests * Added tests with 6 and 8 inverters

* tests if the directory structure of the source is maintained in the output * tests if output for files in subdirectories are generated as expected

* updated any filenames and links that have changed * mentioned the use of Mako syntax

…module

msaligane · 2023-06-16T05:16:08Z

@saicharan0112 thanks! Any comments?

saicharan0112

The CI is passing and I see that temp-sense-gen CI is expecting files where it needs to be, so I can approve my changes based on these things.

harshkhandeparkar added 21 commits May 27, 2023 23:49

feat: added mako to Python requirements.txt

832f830

feat: exported a verilog generation function

45d2c60

doc: added code hints to verilog generation functions

7c58dbd

feat: use the new verilog generation function in temp-sense-gen.

60d11e9

feat: converted temp-sense-gen Verilog to Mako templates

5b4363e

fix: fixed typos in TEMP_ANALOG_lv.v

d305499

fix: changed placeholder port nbout to X

98fb956

feat: updated gitignore files

688859b

fix: removed unused imports in temp-sense-gen.py

5e18789

fix: removed extra tabs in Verilog source

ac85fb9

fix: removed a statement which incremented ninv

1a3bbd6

feat: commented unused code

ef5a28f

feat: added designName as a parameter in the Verilog source

9524faf

feat: designName parameter code

3d74ba4

* uncommented code which inserts the designName in config.mk * removed code which inserts the designName parameter in Verilog

feat: removed previous code

835b9b6

* removed previous code used to generate output Verilog * removed previous code used to copy generated Verilog

feat: removed .template replacement

441f004

* removed code which replaces `.template` in source Verilog filenames because it seemed unncessary

refactor: rename counter_generic.v to counter.v

a55f30f

because it's output filename is the same as the input filename

feat: clean the generated verilog files in make clean

eef004f

docs: added docstrings to common API

70c120e

* added docstring to the __init__.py file * added docstrings to the functions defined in verilog_generation module

feat: pre-imported common defs

115747f

* added commonly used Verilog functions as defs in the Mako template * updated the source verilog code to use the new defs * added a TODO: comment to improve this way of importing defs in the future

feat: removed old commented Verilog code

67660e9

msaligane requested a review from saicharan0112 May 31, 2023 13:13

fix: fixed generation of blocks/sky130hd/*.txt

c8e8518

* uncommented code for generating `blocks/sky130hd/tempsenseInst_custom_net.txt` and `blocks/sky130hd/tempsenseInst_domain_insts.txt` files * updated the source file path to reflect the changes in Verilog generation

alibillalhammoud approved these changes Jun 5, 2023

View reviewed changes

refactor: convert all class privates to module privates

6d38d10

* renamed all functions beginning with double _ to single _ to make them accessible using import <module_name>

harshkhandeparkar added 3 commits June 5, 2023 21:30

test: added unit tests for the _generate_file function

677bf9f

* Added unit tests using pytest in test/ directory * Used part of temp-sense-gen Verilog for unit tests * Added tests with 6 and 8 inverters

test: added better error message in asserts

d97616b

test: added tests for files in subdirectory

2e5dda3

* tests if the directory structure of the source is maintained in the output * tests if output for files in subdirectories are generated as expected

harshkhandeparkar added 4 commits June 7, 2023 23:42

docs: update flow-tempsense.rst to reflect the changes

cc0f3b5

* updated any filenames and links that have changed * mentioned the use of Mako syntax

feat: export a map of common platform prefixes in verilog_generation …

a0e4ee4

…module

feat: used the exported prefix map in temp sensor

07eab48

docs: added docstrings for the prefix map

32f6336

saicharan0112 approved these changes Jun 16, 2023

View reviewed changes

harshkhandeparkar added 2 commits June 21, 2023 15:28

docs: added common python module docs to sphinx documentation

d8cd281

docs: mention the Common Python API in tempsense docs

cbf4381

msaligane approved these changes Jul 18, 2023

View reviewed changes

msaligane merged commit e421346 into idea-fasoc:main Jul 18, 2023
8 checks passed

This was referenced Aug 3, 2023

[GSoC] Common Python API #211

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[GSoC] Common Verilog Generation API and Implementation in `temp-sense-gen` #212

[GSoC] Common Verilog Generation API and Implementation in `temp-sense-gen` #212

harshkhandeparkar commented May 31, 2023 •

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msaligane commented May 31, 2023

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saicharan0112 commented Jun 5, 2023

msaligane commented Jun 16, 2023

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[GSoC] Common Verilog Generation API and Implementation in temp-sense-gen #212

[GSoC] Common Verilog Generation API and Implementation in temp-sense-gen #212

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harshkhandeparkar commented May 31, 2023 • edited Loading

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msaligane commented May 31, 2023

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saicharan0112 commented Jun 5, 2023

msaligane commented Jun 16, 2023

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[GSoC] Common Verilog Generation API and Implementation in `temp-sense-gen` #212

[GSoC] Common Verilog Generation API and Implementation in `temp-sense-gen` #212

harshkhandeparkar commented May 31, 2023 •

edited

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