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TT results -30 to 125 in 1K steps gds #45: Commit 7b819db pushed by hpretl
January 1, 2024 17:12 30s reduce_design
reduce_design
January 1, 2024 17:12 30s
Adding relevant Verilog sources (so that no confusion exists to where… gds #44: Commit 5c1149c pushed by hpretl
December 30, 2023 19:31 30s reduce_design
reduce_design
December 30, 2023 19:31 30s
Simulation setup for paper sims, can now run effectively vs. temp and… gds #43: Commit 5eca357 pushed by hpretl
December 30, 2023 19:28 32s reduce_design
reduce_design
December 30, 2023 19:28 32s
Reduced design for tempsensor (reducing TinyTapeout overhead, LUT, DB… gds #42: Commit 256b755 pushed by hpretl
December 30, 2023 19:12 33s reduce_design
reduce_design
December 30, 2023 19:12 33s
Xyce TB gds #41: Commit 9b931dc pushed by hpretl
December 30, 2023 17:24 25s reduce_design
reduce_design
December 30, 2023 17:24 25s
Xyce TB gds #40: Commit 9b931dc pushed by hpretl
December 30, 2023 16:40 30s main
main
December 30, 2023 16:40 30s
New TB gds #39: Commit bc491fb pushed by hpretl
December 30, 2023 10:34 26s main
main
December 30, 2023 10:34 26s
Update to TB gds #38: Commit fcf745c pushed by hpretl
December 30, 2023 10:28 26s main
main
December 30, 2023 10:28 26s
Add sim TB gds #37: Commit d37c9ea pushed by hpretl
December 29, 2023 23:50 28s main
main
December 29, 2023 23:50 28s
Update sim environment gds #36: Commit 5cd48e3 pushed by hpretl
December 29, 2023 23:44 24s main
main
December 29, 2023 23:44 24s
Update tb_tempsens.sch gds #35: Commit 6eca650 pushed by hpretl
December 29, 2023 15:21 29s main
main
December 29, 2023 15:21 29s
DAC simulation TB and results gds #34: Commit 5a75e28 pushed by hpretl
December 29, 2023 14:22 31s sim_paper
sim_paper
December 29, 2023 14:22 31s
Update TB gds #33: Commit 1b4b97c pushed by hpretl
December 28, 2023 09:08 23s sim_paper
sim_paper
December 28, 2023 09:08 23s
Add missing files gds #32: Commit 8488f08 pushed by hpretl
December 28, 2023 09:08 32s sim_paper
sim_paper
December 28, 2023 09:08 32s
First sim results gds #31: Commit 5073518 pushed by hpretl
December 28, 2023 08:03 1m 23s sim_paper
sim_paper
December 28, 2023 08:03 1m 23s
Add models gds #30: Commit f2393a5 pushed by hpretl
December 27, 2023 20:59 1m 15s sim_paper
sim_paper
December 27, 2023 20:59 1m 15s
Setup to simulate results for paper gds #29: Commit 0fa150a pushed by hpretl
December 27, 2023 20:51 1m 17s sim_paper
sim_paper
December 27, 2023 20:51 1m 17s
ci: workaround for broken Cython version gds #28: Commit 6362a08 pushed by hpretl
December 27, 2023 20:48 3m 43s sim_paper
sim_paper
December 27, 2023 20:48 3m 43s