[Clang][XTHeadVector] Implement zvlsseg unit-stride variant (ruyisdk#131

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imkiva · Oct 25, 2024 · 6fa58f4 · 6fa58f4
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diff --git a/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td b/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td
diff --git a/...handcrafted/zvlsseg/unit-stride/vlseg2b.c → ...afted/zvlsseg/unit-stride/thead/vlseg2b.c b/...handcrafted/zvlsseg/unit-stride/vlseg2b.c → ...afted/zvlsseg/unit-stride/thead/vlseg2b.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg2e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg2e16.c b/...ndcrafted/zvlsseg/unit-stride/vlseg2e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg2e16.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg2e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg2e16ff.c b/...crafted/zvlsseg/unit-stride/vlseg2e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg2e16ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg2e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg2e32.c b/...ndcrafted/zvlsseg/unit-stride/vlseg2e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg2e32.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg2e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg2e32ff.c b/...crafted/zvlsseg/unit-stride/vlseg2e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg2e32ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg2e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg2e64.c b/...ndcrafted/zvlsseg/unit-stride/vlseg2e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg2e64.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg2e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg2e64ff.c b/...crafted/zvlsseg/unit-stride/vlseg2e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg2e64ff.c
diff --git a/...andcrafted/zvlsseg/unit-stride/vlseg2e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg2e8.c b/...andcrafted/zvlsseg/unit-stride/vlseg2e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg2e8.c
diff --git a/...dcrafted/zvlsseg/unit-stride/vlseg2e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg2e8ff.c b/...dcrafted/zvlsseg/unit-stride/vlseg2e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg2e8ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg3e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg3e16.c b/...ndcrafted/zvlsseg/unit-stride/vlseg3e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg3e16.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg3e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg3e16ff.c b/...crafted/zvlsseg/unit-stride/vlseg3e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg3e16ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg3e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg3e32.c b/...ndcrafted/zvlsseg/unit-stride/vlseg3e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg3e32.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg3e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg3e32ff.c b/...crafted/zvlsseg/unit-stride/vlseg3e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg3e32ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg3e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg3e64.c b/...ndcrafted/zvlsseg/unit-stride/vlseg3e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg3e64.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg3e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg3e64ff.c b/...crafted/zvlsseg/unit-stride/vlseg3e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg3e64ff.c
diff --git a/...andcrafted/zvlsseg/unit-stride/vlseg3e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg3e8.c b/...andcrafted/zvlsseg/unit-stride/vlseg3e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg3e8.c
diff --git a/...dcrafted/zvlsseg/unit-stride/vlseg3e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg3e8ff.c b/...dcrafted/zvlsseg/unit-stride/vlseg3e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg3e8ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg4e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg4e16.c b/...ndcrafted/zvlsseg/unit-stride/vlseg4e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg4e16.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg4e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg4e16ff.c b/...crafted/zvlsseg/unit-stride/vlseg4e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg4e16ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg4e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg4e32.c b/...ndcrafted/zvlsseg/unit-stride/vlseg4e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg4e32.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg4e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg4e32ff.c b/...crafted/zvlsseg/unit-stride/vlseg4e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg4e32ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg4e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg4e64.c b/...ndcrafted/zvlsseg/unit-stride/vlseg4e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg4e64.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg4e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg4e64ff.c b/...crafted/zvlsseg/unit-stride/vlseg4e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg4e64ff.c
diff --git a/...andcrafted/zvlsseg/unit-stride/vlseg4e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg4e8.c b/...andcrafted/zvlsseg/unit-stride/vlseg4e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg4e8.c
diff --git a/...dcrafted/zvlsseg/unit-stride/vlseg4e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg4e8ff.c b/...dcrafted/zvlsseg/unit-stride/vlseg4e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg4e8ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg5e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg5e16.c b/...ndcrafted/zvlsseg/unit-stride/vlseg5e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg5e16.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg5e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg5e16ff.c b/...crafted/zvlsseg/unit-stride/vlseg5e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg5e16ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg5e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg5e32.c b/...ndcrafted/zvlsseg/unit-stride/vlseg5e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg5e32.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg5e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg5e32ff.c b/...crafted/zvlsseg/unit-stride/vlseg5e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg5e32ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg5e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg5e64.c b/...ndcrafted/zvlsseg/unit-stride/vlseg5e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg5e64.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg5e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg5e64ff.c b/...crafted/zvlsseg/unit-stride/vlseg5e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg5e64ff.c
diff --git a/...andcrafted/zvlsseg/unit-stride/vlseg5e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg5e8.c b/...andcrafted/zvlsseg/unit-stride/vlseg5e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg5e8.c
diff --git a/...dcrafted/zvlsseg/unit-stride/vlseg5e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg5e8ff.c b/...dcrafted/zvlsseg/unit-stride/vlseg5e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg5e8ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg6e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg6e16.c b/...ndcrafted/zvlsseg/unit-stride/vlseg6e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg6e16.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg6e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg6e16ff.c b/...crafted/zvlsseg/unit-stride/vlseg6e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg6e16ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg6e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg6e32.c b/...ndcrafted/zvlsseg/unit-stride/vlseg6e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg6e32.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg6e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg6e32ff.c b/...crafted/zvlsseg/unit-stride/vlseg6e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg6e32ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg6e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg6e64.c b/...ndcrafted/zvlsseg/unit-stride/vlseg6e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg6e64.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg6e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg6e64ff.c b/...crafted/zvlsseg/unit-stride/vlseg6e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg6e64ff.c
diff --git a/...andcrafted/zvlsseg/unit-stride/vlseg6e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg6e8.c b/...andcrafted/zvlsseg/unit-stride/vlseg6e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg6e8.c
diff --git a/...dcrafted/zvlsseg/unit-stride/vlseg6e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg6e8ff.c b/...dcrafted/zvlsseg/unit-stride/vlseg6e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg6e8ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg7e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg7e16.c b/...ndcrafted/zvlsseg/unit-stride/vlseg7e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg7e16.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg7e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg7e16ff.c b/...crafted/zvlsseg/unit-stride/vlseg7e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg7e16ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg7e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg7e32.c b/...ndcrafted/zvlsseg/unit-stride/vlseg7e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg7e32.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg7e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg7e32ff.c b/...crafted/zvlsseg/unit-stride/vlseg7e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg7e32ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg7e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg7e64.c b/...ndcrafted/zvlsseg/unit-stride/vlseg7e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg7e64.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg7e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg7e64ff.c b/...crafted/zvlsseg/unit-stride/vlseg7e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg7e64ff.c
diff --git a/...andcrafted/zvlsseg/unit-stride/vlseg7e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg7e8.c b/...andcrafted/zvlsseg/unit-stride/vlseg7e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg7e8.c
diff --git a/...dcrafted/zvlsseg/unit-stride/vlseg7e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg7e8ff.c b/...dcrafted/zvlsseg/unit-stride/vlseg7e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg7e8ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg8e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg8e16.c b/...ndcrafted/zvlsseg/unit-stride/vlseg8e16.c → ...ted/zvlsseg/unit-stride/thead/vlseg8e16.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg8e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg8e16ff.c b/...crafted/zvlsseg/unit-stride/vlseg8e16ff.c → ...d/zvlsseg/unit-stride/thead/vlseg8e16ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg8e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg8e32.c b/...ndcrafted/zvlsseg/unit-stride/vlseg8e32.c → ...ted/zvlsseg/unit-stride/thead/vlseg8e32.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg8e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg8e32ff.c b/...crafted/zvlsseg/unit-stride/vlseg8e32ff.c → ...d/zvlsseg/unit-stride/thead/vlseg8e32ff.c
diff --git a/...ndcrafted/zvlsseg/unit-stride/vlseg8e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg8e64.c b/...ndcrafted/zvlsseg/unit-stride/vlseg8e64.c → ...ted/zvlsseg/unit-stride/thead/vlseg8e64.c
diff --git a/...crafted/zvlsseg/unit-stride/vlseg8e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg8e64ff.c b/...crafted/zvlsseg/unit-stride/vlseg8e64ff.c → ...d/zvlsseg/unit-stride/thead/vlseg8e64ff.c
diff --git a/...andcrafted/zvlsseg/unit-stride/vlseg8e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg8e8.c b/...andcrafted/zvlsseg/unit-stride/vlseg8e8.c → ...fted/zvlsseg/unit-stride/thead/vlseg8e8.c
diff --git a/...dcrafted/zvlsseg/unit-stride/vlseg8e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg8e8ff.c b/...dcrafted/zvlsseg/unit-stride/vlseg8e8ff.c → ...ed/zvlsseg/unit-stride/thead/vlseg8e8ff.c
diff --git a/...g/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e16.c b/...g/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e16.c
diff --git a/...g/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e32.c b/...g/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e32.c
diff --git a/...g/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e64.c b/...g/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e64.c
diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e8.c
@@ -0,0 +1,176 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN:   opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m1x2
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 8 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 8 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } poison, <vscale x 8 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], <vscale x 8 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.nxv8i8.i64(<vscale x 8 x i8> [[TMP2]], <vscale x 8 x i8> [[TMP3]], ptr [[BASE]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_i8m1x2(int8_t *base, vint8m1x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_i8m1x2(base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m2x2
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 16 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 16 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.nxv16i8.i64(<vscale x 16 x i8> [[TMP2]], <vscale x 16 x i8> [[TMP3]], ptr [[BASE]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_i8m2x2(int8_t *base, vint8m2x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_i8m2x2(base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m4x2
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 32 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 32 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } poison, <vscale x 32 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], <vscale x 32 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.nxv32i8.i64(<vscale x 32 x i8> [[TMP2]], <vscale x 32 x i8> [[TMP3]], ptr [[BASE]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_i8m4x2(int8_t *base, vint8m4x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_i8m4x2(base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m1x2
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 8 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 8 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } poison, <vscale x 8 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], <vscale x 8 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.nxv8i8.i64(<vscale x 8 x i8> [[TMP2]], <vscale x 8 x i8> [[TMP3]], ptr [[BASE]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_u8m1x2(uint8_t *base, vuint8m1x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_u8m1x2(base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m2x2
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 16 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 16 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.nxv16i8.i64(<vscale x 16 x i8> [[TMP2]], <vscale x 16 x i8> [[TMP3]], ptr [[BASE]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_u8m2x2(uint8_t *base, vuint8m2x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_u8m2x2(base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m4x2
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 32 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 32 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } poison, <vscale x 32 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], <vscale x 32 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.nxv32i8.i64(<vscale x 32 x i8> [[TMP2]], <vscale x 32 x i8> [[TMP3]], ptr [[BASE]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_u8m4x2(uint8_t *base, vuint8m4x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_u8m4x2(base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m1x2_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 8 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 8 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } poison, <vscale x 8 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], <vscale x 8 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP2]], <vscale x 8 x i8> [[TMP3]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_i8m1x2_m(vbool8_t mask, int8_t *base, vint8m1x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_i8m1x2_m(mask, base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m2x2_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 16 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 16 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP2]], <vscale x 16 x i8> [[TMP3]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_i8m2x2_m(vbool4_t mask, int8_t *base, vint8m2x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_i8m2x2_m(mask, base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m4x2_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 32 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 32 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } poison, <vscale x 32 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], <vscale x 32 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.mask.nxv32i8.i64(<vscale x 32 x i8> [[TMP2]], <vscale x 32 x i8> [[TMP3]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_i8m4x2_m(vbool2_t mask, int8_t *base, vint8m4x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_i8m4x2_m(mask, base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m1x2_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 8 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 8 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } poison, <vscale x 8 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], <vscale x 8 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP2]], <vscale x 8 x i8> [[TMP3]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_u8m1x2_m(vbool8_t mask, uint8_t *base, vuint8m1x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_u8m1x2_m(mask, base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m2x2_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 16 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 16 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP2]], <vscale x 16 x i8> [[TMP3]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_u8m2x2_m(vbool4_t mask, uint8_t *base, vuint8m2x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_u8m2x2_m(mask, base, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m4x2_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 32 x i8> [[V_TUPLE_COERCE0:%.*]], <vscale x 32 x i8> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } poison, <vscale x 32 x i8> [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], <vscale x 32 x i8> [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP1]], 1
+// CHECK-RV64-NEXT:    call void @llvm.riscv.th.vsseg2e.mask.nxv32i8.i64(<vscale x 32 x i8> [[TMP2]], <vscale x 32 x i8> [[TMP3]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_th_vsseg2e8_v_u8m4x2_m(vbool2_t mask, uint8_t *base, vuint8m4x2_t v_tuple, size_t vl) {
+  return __riscv_th_vsseg2e8_v_u8m4x2_m(mask, base, v_tuple, vl);
+}
+