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[LLVM] [RVV 0.7.1] Temporarily disable vamo (ruyisdk#21)
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intrinsics.
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@AinsleySnow
AinsleySnow authored Nov 6, 2023
1 parent 2799eb9 commit 7abf730
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60 changes: 30 additions & 30 deletions llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -37,36 +37,36 @@ let TargetPrefix = "riscv" in {

} // TargetPrefix = "riscv"

let TargetPrefix = "riscv" in {
// 8. Vector AMO Operations (Zvamo)
// let TargetPrefix = "riscv" in {
// // 8. Vector AMO Operations (Zvamo)

// For atomic operations without mask
// Input: (base pointer, index, value, vl)
class XVAMONoMask
: Intrinsic<[llvm_anyvector_ty],
[llvm_ptr_ty, llvm_anyvector_ty, LLVMMatchType<0>,
llvm_anyint_ty],
[NoCapture<ArgIndex<0>>]>, RISCVVIntrinsic;
// For atomic operations with mask
// Input: (base pointer, index, value, mask, vl)
class XVAMOMask
: Intrinsic<[llvm_anyvector_ty],
[llvm_ptr_ty, llvm_anyvector_ty, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[NoCapture<ArgIndex<0>>]>, RISCVVIntrinsic;
// // For atomic operations without mask
// // Input: (base pointer, index, value, vl)
// class XVAMONoMask
// : Intrinsic<[llvm_anyvector_ty],
// [llvm_ptr_ty, llvm_anyvector_ty, LLVMMatchType<0>,
// llvm_anyint_ty],
// [NoCapture<ArgIndex<0>>]>, RISCVVIntrinsic;
// // For atomic operations with mask
// // Input: (base pointer, index, value, mask, vl)
// class XVAMOMask
// : Intrinsic<[llvm_anyvector_ty],
// [llvm_ptr_ty, llvm_anyvector_ty, LLVMMatchType<0>,
// LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
// [NoCapture<ArgIndex<0>>]>, RISCVVIntrinsic;

multiclass XIntrinsicVAMO {
def "int_riscv_" # NAME : XVAMONoMask;
def "int_riscv_" # NAME # "_mask" : XVAMOMask;
}
// multiclass XIntrinsicVAMO {
// def "int_riscv_" # NAME : XVAMONoMask;
// def "int_riscv_" # NAME # "_mask" : XVAMOMask;
// }

defm xvamoswap : XIntrinsicVAMO;
defm xvamoadd : XIntrinsicVAMO;
defm xvamoxor : XIntrinsicVAMO;
defm xvamoand : XIntrinsicVAMO;
defm xvamoor : XIntrinsicVAMO;
defm xvamomin : XIntrinsicVAMO;
defm xvamomax : XIntrinsicVAMO;
defm xvamominu : XIntrinsicVAMO;
defm xvamomaxu : XIntrinsicVAMO;
} // TargetPrefix = "riscv"
// defm xvamoswap : XIntrinsicVAMO;
// defm xvamoadd : XIntrinsicVAMO;
// defm xvamoxor : XIntrinsicVAMO;
// defm xvamoand : XIntrinsicVAMO;
// defm xvamoor : XIntrinsicVAMO;
// defm xvamomin : XIntrinsicVAMO;
// defm xvamomax : XIntrinsicVAMO;
// defm xvamominu : XIntrinsicVAMO;
// defm xvamomaxu : XIntrinsicVAMO;
// } // TargetPrefix = "riscv"
300 changes: 150 additions & 150 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td
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Original file line number Diff line number Diff line change
Expand Up @@ -95,78 +95,78 @@ let Predicates = [HasVendorXTHeadV] in {
//===----------------------------------------------------------------------===//

// Pseudo base class for unmasked vamo instructions
class XVPseudoAMOWDNoMask<VReg RetClass,
VReg Op1Class> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
(ins Op1Class:$vs2,
GPR:$rs1,
GetVRegNoV0<RetClass>.R:$vd,
AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 1;
let mayStore = 1;
let hasSideEffects = 1;
let Constraints = "$vd_wd = $vd";
let HasVLOp = 1;
let HasSEWOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst # "_V");
}
// class XVPseudoAMOWDNoMask<VReg RetClass,
// VReg Op1Class> :
// Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
// (ins Op1Class:$vs2,
// GPR:$rs1,
// GetVRegNoV0<RetClass>.R:$vd,
// AVL:$vl, ixlenimm:$sew), []>,
// RISCVVPseudo {
// let mayLoad = 1;
// let mayStore = 1;
// let hasSideEffects = 1;
// let Constraints = "$vd_wd = $vd";
// let HasVLOp = 1;
// let HasSEWOp = 1;
// let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst # "_V");
// }

// Pseudo base class for masked vamo instructions
class XVPseudoAMOWDMask<VReg RetClass,
VReg Op1Class> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
(ins Op1Class:$vs2,
GPR:$rs1,
GetVRegNoV0<RetClass>.R:$vd,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 1;
let mayStore = 1;
let hasSideEffects = 1;
let Constraints = "$vd_wd = $vd";
let HasVLOp = 1;
let HasSEWOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst # "_V");
}
// // Pseudo base class for masked vamo instructions
// class XVPseudoAMOWDMask<VReg RetClass,
// VReg Op1Class> :
// Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
// (ins Op1Class:$vs2,
// GPR:$rs1,
// GetVRegNoV0<RetClass>.R:$vd,
// VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
// RISCVVPseudo {
// let mayLoad = 1;
// let mayStore = 1;
// let hasSideEffects = 1;
// let Constraints = "$vd_wd = $vd";
// let HasVLOp = 1;
// let HasSEWOp = 1;
// let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst # "_V");
// }

multiclass XVPseudoAMOMem<int mem> {
// VAMO in RVV 0.7.1 supports 32, 64, and 128 Mem data bits, and in
// the base vector "V" extension, only SEW up to ELEN = max(XLEN, FLEN)
// are required to be supported, therefore only [32, 64] is allowed here.
foreach sew = [32, 64] in {
foreach lmul = [V_M1, V_M2, V_M4, V_M8] in {
defvar octuple_lmul = lmul.octuple;
// Calculate emul = sew * lmul / mem
defvar octuple_emul = !srl(!mul(sew, octuple_lmul), !logtwo(mem));
if !and(!ge(octuple_emul, 8), !le(octuple_emul, 64)) then {
defvar emulMX = octuple_to_str<octuple_emul>.ret;
defvar emul = !cast<LMULInfo>("V_" # emulMX);
let VLMul = lmul.value in {
def "_WD_" # lmul.MX # "_" # emulMX : XVPseudoAMOWDNoMask<lmul.vrclass, emul.vrclass>;
def "_WD_" # lmul.MX # "_" # emulMX # "_MASK" : XVPseudoAMOWDMask<lmul.vrclass, emul.vrclass>;
}
}
}
}
}
// multiclass XVPseudoAMOMem<int mem> {
// // VAMO in RVV 0.7.1 supports 32, 64, and 128 Mem data bits, and in
// // the base vector "V" extension, only SEW up to ELEN = max(XLEN, FLEN)
// // are required to be supported, therefore only [32, 64] is allowed here.
// foreach sew = [32, 64] in {
// foreach lmul = [V_M1, V_M2, V_M4, V_M8] in {
// defvar octuple_lmul = lmul.octuple;
// // Calculate emul = sew * lmul / mem
// defvar octuple_emul = !srl(!mul(sew, octuple_lmul), !logtwo(mem));
// if !and(!ge(octuple_emul, 8), !le(octuple_emul, 64)) then {
// defvar emulMX = octuple_to_str<octuple_emul>.ret;
// defvar emul = !cast<LMULInfo>("V_" # emulMX);
// let VLMul = lmul.value in {
// def "_WD_" # lmul.MX # "_" # emulMX : XVPseudoAMOWDNoMask<lmul.vrclass, emul.vrclass>;
// def "_WD_" # lmul.MX # "_" # emulMX # "_MASK" : XVPseudoAMOWDMask<lmul.vrclass, emul.vrclass>;
// }
// }
// }
// }
// }

multiclass XVPseudoAMO {
defm "W" : XVPseudoAMOMem<32>;
defm "D" : XVPseudoAMOMem<64>;
}
// multiclass XVPseudoAMO {
// defm "W" : XVPseudoAMOMem<32>;
// defm "D" : XVPseudoAMOMem<64>;
// }

let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in {
defm PseudoXVAMOSWAP : XVPseudoAMO;
defm PseudoXVAMOADD : XVPseudoAMO;
defm PseudoXVAMOXOR : XVPseudoAMO;
defm PseudoXVAMOAND : XVPseudoAMO;
defm PseudoXVAMOOR : XVPseudoAMO;
defm PseudoXVAMOMIN : XVPseudoAMO;
defm PseudoXVAMOMAX : XVPseudoAMO;
defm PseudoXVAMOMINU : XVPseudoAMO;
defm PseudoXVAMOMAXU : XVPseudoAMO;
} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA]
// let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in {
// defm PseudoXVAMOSWAP : XVPseudoAMO;
// defm PseudoXVAMOADD : XVPseudoAMO;
// defm PseudoXVAMOXOR : XVPseudoAMO;
// defm PseudoXVAMOAND : XVPseudoAMO;
// defm PseudoXVAMOOR : XVPseudoAMO;
// defm PseudoXVAMOMIN : XVPseudoAMO;
// defm PseudoXVAMOMAX : XVPseudoAMO;
// defm PseudoXVAMOMINU : XVPseudoAMO;
// defm PseudoXVAMOMAXU : XVPseudoAMO;
// } // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA]

// TODO: try to reuse them from RISCVInstrInfoVPseudos.td, see the `HasStdVOrXTHeadV` predicate
//===----------------------------------------------------------------------===//
Expand All @@ -185,89 +185,89 @@ let Predicates = [HasVendorXTHeadV] in {
} // Predicates = [HasVendorXTHeadV]

// Patterns for vamo intrinsics.
class XVPatAMOWDNoMask<string intrinsic_name,
string inst,
ValueType result_type,
ValueType op1_type,
int sew,
LMULInfo vlmul,
LMULInfo emul,
VReg op1_reg_class> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
GPR:$rs1,
(op1_type op1_reg_class:$vs2),
(result_type vlmul.vrclass:$vd),
VLOpFrag)),
(!cast<Instruction>(inst # "_WD_" # vlmul.MX # "_" # emul.MX)
$vs2, $rs1, $vd,
GPR:$vl, sew)>;
// class XVPatAMOWDNoMask<string intrinsic_name,
// string inst,
// ValueType result_type,
// ValueType op1_type,
// int sew,
// LMULInfo vlmul,
// LMULInfo emul,
// VReg op1_reg_class> :
// Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
// GPR:$rs1,
// (op1_type op1_reg_class:$vs2),
// (result_type vlmul.vrclass:$vd),
// VLOpFrag)),
// (!cast<Instruction>(inst # "_WD_" # vlmul.MX # "_" # emul.MX)
// $vs2, $rs1, $vd,
// GPR:$vl, sew)>;

class XVPatAMOWDMask<string intrinsic_name,
string inst,
ValueType result_type,
ValueType op1_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
LMULInfo emul,
VReg op1_reg_class> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name # "_mask")
GPR:$rs1,
(op1_type op1_reg_class:$vs2),
(result_type vlmul.vrclass:$vd),
(mask_type V0),
VLOpFrag)),
(!cast<Instruction>(inst # "_WD_" # vlmul.MX # "_" # emul.MX # "_MASK")
$vs2, $rs1, $vd,
(mask_type V0), GPR:$vl, sew)>;
// class XVPatAMOWDMask<string intrinsic_name,
// string inst,
// ValueType result_type,
// ValueType op1_type,
// ValueType mask_type,
// int sew,
// LMULInfo vlmul,
// LMULInfo emul,
// VReg op1_reg_class> :
// Pat<(result_type (!cast<Intrinsic>(intrinsic_name # "_mask")
// GPR:$rs1,
// (op1_type op1_reg_class:$vs2),
// (result_type vlmul.vrclass:$vd),
// (mask_type V0),
// VLOpFrag)),
// (!cast<Instruction>(inst # "_WD_" # vlmul.MX # "_" # emul.MX # "_MASK")
// $vs2, $rs1, $vd,
// (mask_type V0), GPR:$vl, sew)>;

multiclass XVPatAMOWD<string intrinsic,
string inst,
ValueType result_type,
ValueType offset_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
LMULInfo emul,
VReg op1_reg_class> {
def : XVPatAMOWDNoMask<intrinsic, inst, result_type, offset_type,
sew, vlmul, emul, op1_reg_class>;
def : XVPatAMOWDMask<intrinsic, inst, result_type, offset_type,
mask_type, sew, vlmul, emul, op1_reg_class>;
}
// multiclass XVPatAMOWD<string intrinsic,
// string inst,
// ValueType result_type,
// ValueType offset_type,
// ValueType mask_type,
// int sew,
// LMULInfo vlmul,
// LMULInfo emul,
// VReg op1_reg_class> {
// def : XVPatAMOWDNoMask<intrinsic, inst, result_type, offset_type,
// sew, vlmul, emul, op1_reg_class>;
// def : XVPatAMOWDMask<intrinsic, inst, result_type, offset_type,
// mask_type, sew, vlmul, emul, op1_reg_class>;
// }

multiclass XVPatAMOV_WD<string intrinsic,
string inst,
list<VTypeInfo> vtilist> {
foreach eew = [32, 64] in {
foreach vti = vtilist in {
if !or(!eq(vti.SEW, 32), !eq(vti.SEW, 64)) then {
defvar octuple_lmul = vti.LMul.octuple;
// Calculate emul = eew * lmul / sew
defvar octuple_emul = !srl(!mul(eew, octuple_lmul), vti.Log2SEW);
// emul must be in range 8 - 64, since rvv 0.7.1 does not
// allow fractional lmul
if !and(!ge(octuple_emul, 8), !le(octuple_emul, 64)) then {
defvar emulMX = octuple_to_str<octuple_emul>.ret;
defvar offsetVti = !cast<VTypeInfo>("XVI" # eew # emulMX);
defvar inst_tag = inst # !cond(!eq(vti.SEW, 32) : "W", !eq(vti.SEW, 64) : "D");
defm : XVPatAMOWD<intrinsic, inst_tag,
vti.Vector, offsetVti.Vector,
vti.Mask, vti.Log2SEW, vti.LMul, offsetVti.LMul, offsetVti.RegClass>;
}
}
}
}
}
// multiclass XVPatAMOV_WD<string intrinsic,
// string inst,
// list<VTypeInfo> vtilist> {
// foreach eew = [32, 64] in {
// foreach vti = vtilist in {
// if !or(!eq(vti.SEW, 32), !eq(vti.SEW, 64)) then {
// defvar octuple_lmul = vti.LMul.octuple;
// // Calculate emul = eew * lmul / sew
// defvar octuple_emul = !srl(!mul(eew, octuple_lmul), vti.Log2SEW);
// // emul must be in range 8 - 64, since rvv 0.7.1 does not
// // allow fractional lmul
// if !and(!ge(octuple_emul, 8), !le(octuple_emul, 64)) then {
// defvar emulMX = octuple_to_str<octuple_emul>.ret;
// defvar offsetVti = !cast<VTypeInfo>("XVI" # eew # emulMX);
// defvar inst_tag = inst # !cond(!eq(vti.SEW, 32) : "W", !eq(vti.SEW, 64) : "D");
// defm : XVPatAMOWD<intrinsic, inst_tag,
// vti.Vector, offsetVti.Vector,
// vti.Mask, vti.Log2SEW, vti.LMul, offsetVti.LMul, offsetVti.RegClass>;
// }
// }
// }
// }
// }

let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in {
defm : XVPatAMOV_WD<"int_riscv_xvamoswap", "PseudoXVAMOSWAP", AllIntegerXVectors>;
defm : XVPatAMOV_WD<"int_riscv_xvamoadd", "PseudoXVAMOADD", AllIntegerXVectors>;
defm : XVPatAMOV_WD<"int_riscv_xvamoxor", "PseudoXVAMOXOR", AllIntegerXVectors>;
defm : XVPatAMOV_WD<"int_riscv_xvamoand", "PseudoXVAMOAND", AllIntegerXVectors>;
defm : XVPatAMOV_WD<"int_riscv_xvamoor", "PseudoXVAMOOR", AllIntegerXVectors>;
defm : XVPatAMOV_WD<"int_riscv_xvamomin", "PseudoXVAMOMIN", AllIntegerXVectors>;
defm : XVPatAMOV_WD<"int_riscv_xvamomax", "PseudoXVAMOMAX", AllIntegerXVectors>;
defm : XVPatAMOV_WD<"int_riscv_xvamominu", "PseudoXVAMOMINU", AllIntegerXVectors>;
defm : XVPatAMOV_WD<"int_riscv_xvamomaxu", "PseudoXVAMOMAXU", AllIntegerXVectors>;
} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA]
// let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in {
// defm : XVPatAMOV_WD<"int_riscv_xvamoswap", "PseudoXVAMOSWAP", AllIntegerXVectors>;
// defm : XVPatAMOV_WD<"int_riscv_xvamoadd", "PseudoXVAMOADD", AllIntegerXVectors>;
// defm : XVPatAMOV_WD<"int_riscv_xvamoxor", "PseudoXVAMOXOR", AllIntegerXVectors>;
// defm : XVPatAMOV_WD<"int_riscv_xvamoand", "PseudoXVAMOAND", AllIntegerXVectors>;
// defm : XVPatAMOV_WD<"int_riscv_xvamoor", "PseudoXVAMOOR", AllIntegerXVectors>;
// defm : XVPatAMOV_WD<"int_riscv_xvamomin", "PseudoXVAMOMIN", AllIntegerXVectors>;
// defm : XVPatAMOV_WD<"int_riscv_xvamomax", "PseudoXVAMOMAX", AllIntegerXVectors>;
// defm : XVPatAMOV_WD<"int_riscv_xvamominu", "PseudoXVAMOMINU", AllIntegerXVectors>;
// defm : XVPatAMOV_WD<"int_riscv_xvamomaxu", "PseudoXVAMOMAXU", AllIntegerXVectors>;
// } // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA]
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