Skip to content

Commit

Permalink
[RVV 0.7.1] port assembler tests from binutils (ruyisdk#6)
Browse files Browse the repository at this point in the history 
* [RVV 0.7.1] add assembler tests from binutils

* [RVV 0.7.1] normalize some register names

* [RVV 0.7.1] insert FileCheck lines

* [RVV 0.7.1] fix `CHECK-INST`

* [RVV 0.7.1] fix `vadc`, `vmadc`, `vsbc`, `vmsbc`

* [RVV 0.7.1] fix `vwmaccsu`, `vwmaccus`

* [RVV 0.7.1] pass all tests from binutils

* [RVV 0.7.1] fix MC test `rvv0p71/add.s`

* [RVV 0.7.1] fix MC test `rvv0p71/sub.s`

* [RVV 0.7.1] fix MC test `rvv0p71/macc.s`

* [RVV 0.7.1] sync the newest tests
  • Loading branch information
@imkiva
imkiva committed Apr 1, 2024
1 parent 93caea7 commit bd5ad97
Show file tree
Hide file tree
Showing 5 changed files with 7,051 additions and 82 deletions.
56 changes: 48 additions & 8 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -164,6 +164,48 @@ multiclass XVNSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
ReadVMask]>;
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// rvv 0.7.1 set vm=1 for `op vd, vs2, vs1, v0`
class XVALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd),
(ins VR:$vs2, VR:$vs1, VMV0:$v0),
opcodestr, "$vd, $vs2, $vs1, v0"> {
let vm = 1;
}

// rvv 0.7.1 set vm=1 for `op vd, vs2, rs1, v0`
class XVALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVX<funct6, opv, (outs VR:$vd),
(ins VR:$vs2, GPR:$rs1, VMV0:$v0),
opcodestr, "$vd, $vs2, $rs1, v0"> {
let vm = 1;
}

// rvv 0.7.1 set vm=1 for `op vd, vs2, imm, v0`
class XVALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
: RVInstIVI<funct6, (outs VR:$vd),
(ins VR:$vs2, optype:$imm, VMV0:$v0),
opcodestr, "$vd, $vs2, $imm, v0"> {
let vm = 1;
}

multiclass XVALUm_IV_V_X<string opcodestr, bits<6> funct6> {
def VM : XVALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
Sched<[WriteVICALUV_WorstCase, ReadVICALUV_WorstCase,
ReadVICALUV_WorstCase, ReadVMask]>;
def XM : XVALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
Sched<[WriteVICALUX_WorstCase, ReadVICALUV_WorstCase,
ReadVICALUX_WorstCase, ReadVMask]>;
}

multiclass XVALUm_IV_V_X_I<string opcodestr, bits<6> funct6>
: XVALUm_IV_V_X<opcodestr, funct6> {
def IM : XVALUmVI<funct6, opcodestr # ".vim">,
Sched<[WriteVICALUI_WorstCase, ReadVICALUV_WorstCase,
ReadVMask]>;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0

//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -314,15 +356,13 @@ defm XVWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">;
} // Constraints = "@earlyclobber $vd"

// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
defm XVADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;
defm XVADC_V : XVALUm_IV_V_X_I<"vadc", 0b010000>;
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
defm XVMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
defm XVMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>;
defm XVMADC_V : XVALUm_IV_V_X_I<"vmadc", 0b010001>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
defm XVSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>;
defm XVSBC_V : XVALUm_IV_V_X<"vsbc", 0b010010>;
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
defm XVMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>;
defm XVMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>;
defm XVMSBC_V : XVALUm_IV_V_X<"vmsbc", 0b010011>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint

// Vector Bitwise Logical Instructions
Expand Down Expand Up @@ -392,8 +432,8 @@ defm XVNMSUB_V : VMAC_MV_V_X<"vnmsub", 0b101011>;
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
defm XVWMACCU_V : VWMAC_MV_V_X<"vwmaccu", 0b111100>;
defm XVWMACC_V : VWMAC_MV_V_X<"vwmacc", 0b111101>;
defm XVWMACCSU_V : VWMAC_MV_V_X<"vwmaccsu", 0b111111>;
defm XVWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111110>;
defm XVWMACCSU_V : VWMAC_MV_V_X<"vwmaccsu", 0b111110>;
defm XVWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111111>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV

// Vector Integer Merge Instructions
Expand Down
54 changes: 18 additions & 36 deletions llvm/test/MC/RISCV/rvv0p71/add.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -142,78 +142,60 @@ vwadd.wx v8, v4, a0

vadc.vvm v8, v4, v20, v0
# CHECK-INST: vadc.vvm v8, v4, v20, v0
# CHECK-ENCODING: [0x57,0x04,0x4a,0x40]
# CHECK-ENCODING: [0x57,0x04,0x4a,0x42]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 04 4a 40 <unknown>
# CHECK-UNKNOWN: 57 04 4a 42 <unknown>

vadc.vvm v4, v4, v20, v0
# CHECK-INST: vadc.vvm v4, v4, v20, v0
# CHECK-ENCODING: [0x57,0x02,0x4a,0x40]
# CHECK-ENCODING: [0x57,0x02,0x4a,0x42]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 02 4a 40 <unknown>
# CHECK-UNKNOWN: 57 02 4a 42 <unknown>

vadc.vvm v8, v4, v8, v0
# CHECK-INST: vadc.vvm v8, v4, v8, v0
# CHECK-ENCODING: [0x57,0x04,0x44,0x40]
# CHECK-ENCODING: [0x57,0x04,0x44,0x42]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 04 44 40 <unknown>
# CHECK-UNKNOWN: 57 04 44 42 <unknown>

vadc.vxm v8, v4, a0, v0
# CHECK-INST: vadc.vxm v8, v4, a0, v0
# CHECK-ENCODING: [0x57,0x44,0x45,0x40]
# CHECK-ENCODING: [0x57,0x44,0x45,0x42]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 44 45 40 <unknown>
# CHECK-UNKNOWN: 57 44 45 42 <unknown>

vadc.vim v8, v4, 15, v0
# CHECK-INST: vadc.vim v8, v4, 15, v0
# CHECK-ENCODING: [0x57,0xb4,0x47,0x40]
# CHECK-ENCODING: [0x57,0xb4,0x47,0x42]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 b4 47 40 <unknown>
# CHECK-UNKNOWN: 57 b4 47 42 <unknown>

vmadc.vvm v8, v4, v20, v0
# CHECK-INST: vmadc.vvm v8, v4, v20, v0
# CHECK-ENCODING: [0x57,0x04,0x4a,0x44]
# CHECK-ENCODING: [0x57,0x04,0x4a,0x46]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 04 4a 44 <unknown>
# CHECK-UNKNOWN: 57 04 4a 46 <unknown>

vmadc.vvm v4, v4, v20, v0
# CHECK-INST: vmadc.vvm v4, v4, v20, v0
# CHECK-ENCODING: [0x57,0x02,0x4a,0x44]
# CHECK-ENCODING: [0x57,0x02,0x4a,0x46]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 02 4a 44 <unknown>
# CHECK-UNKNOWN: 57 02 4a 46 <unknown>

vmadc.vvm v8, v4, v8, v0
# CHECK-INST: vmadc.vvm v8, v4, v8, v0
# CHECK-ENCODING: [0x57,0x04,0x44,0x44]
# CHECK-ENCODING: [0x57,0x04,0x44,0x46]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 04 44 44 <unknown>
# CHECK-UNKNOWN: 57 04 44 46 <unknown>

vmadc.vxm v8, v4, a0, v0
# CHECK-INST: vmadc.vxm v8, v4, a0, v0
# CHECK-ENCODING: [0x57,0x44,0x45,0x44]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 44 45 44 <unknown>

vmadc.vim v8, v4, 15, v0
# CHECK-INST: vmadc.vim v8, v4, 15, v0
# CHECK-ENCODING: [0x57,0xb4,0x47,0x44]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 b4 47 44 <unknown>

vmadc.vv v8, v4, v20
# CHECK-INST: vmadc.vv v8, v4, v20
# CHECK-ENCODING: [0x57,0x04,0x4a,0x46]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 04 4a 46 <unknown>

vmadc.vx v8, v4, a0
# CHECK-INST: vmadc.vx v8, v4, a0
# CHECK-ENCODING: [0x57,0x44,0x45,0x46]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 44 45 46 <unknown>

vmadc.vi v8, v4, 15
# CHECK-INST: vmadc.vi v8, v4, 15
vmadc.vim v8, v4, 15, v0
# CHECK-INST: vmadc.vim v8, v4, 15, v0
# CHECK-ENCODING: [0x57,0xb4,0x47,0x46]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 b4 47 46 <unknown>
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/MC/RISCV/rvv0p71/macc.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -154,39 +154,39 @@ vwmacc.vx v8, a0, v4

vwmaccsu.vv v8, v20, v4, v0.t
# CHECK-INST: vwmaccsu.vv v8, v20, v4, v0.t
# CHECK-ENCODING: [0x57,0x24,0x4a,0xfc]
# CHECK-ENCODING: [0x57,0x24,0x4a,0xf8]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 24 4a fc <unknown>
# CHECK-UNKNOWN: 57 24 4a f8 <unknown>

vwmaccsu.vv v8, v20, v4
# CHECK-INST: vwmaccsu.vv v8, v20, v4
# CHECK-ENCODING: [0x57,0x24,0x4a,0xfe]
# CHECK-ENCODING: [0x57,0x24,0x4a,0xfa]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 24 4a fe <unknown>
# CHECK-UNKNOWN: 57 24 4a fa <unknown>

vwmaccsu.vx v8, a0, v4, v0.t
# CHECK-INST: vwmaccsu.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x57,0x64,0x45,0xfc]
# CHECK-ENCODING: [0x57,0x64,0x45,0xf8]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 64 45 fc <unknown>
# CHECK-UNKNOWN: 57 64 45 f8 <unknown>

vwmaccsu.vx v8, a0, v4
# CHECK-INST: vwmaccsu.vx v8, a0, v4
# CHECK-ENCODING: [0x57,0x64,0x45,0xfe]
# CHECK-ENCODING: [0x57,0x64,0x45,0xfa]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 64 45 fe <unknown>
# CHECK-UNKNOWN: 57 64 45 fa <unknown>

vwmaccus.vx v8, a0, v4, v0.t
# CHECK-INST: vwmaccus.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x57,0x64,0x45,0xf8]
# CHECK-ENCODING: [0x57,0x64,0x45,0xfc]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 64 45 f8 <unknown>
# CHECK-UNKNOWN: 57 64 45 fc <unknown>

vwmaccus.vx v8, a0, v4
# CHECK-INST: vwmaccus.vx v8, a0, v4
# CHECK-ENCODING: [0x57,0x64,0x45,0xfa]
# CHECK-ENCODING: [0x57,0x64,0x45,0xfe]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 64 45 fa <unknown>
# CHECK-UNKNOWN: 57 64 45 fe <unknown>

vwsmaccu.vv v8, v20, v4, v0.t
# CHECK-INST: vwsmaccu.vv v8, v20, v4, v0.t
Expand Down
40 changes: 14 additions & 26 deletions llvm/test/MC/RISCV/rvv0p71/sub.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -154,60 +154,48 @@ vwsub.wx v8, v4, a0

vsbc.vvm v8, v4, v20, v0
# CHECK-INST: vsbc.vvm v8, v4, v20, v0
# CHECK-ENCODING: [0x57,0x04,0x4a,0x48]
# CHECK-ENCODING: [0x57,0x04,0x4a,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 04 4a 48 <unknown>
# CHECK-UNKNOWN: 57 04 4a 4a <unknown>

vsbc.vvm v4, v4, v20, v0
# CHECK-INST: vsbc.vvm v4, v4, v20, v0
# CHECK-ENCODING: [0x57,0x02,0x4a,0x48]
# CHECK-ENCODING: [0x57,0x02,0x4a,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 02 4a 48 <unknown>
# CHECK-UNKNOWN: 57 02 4a 4a <unknown>

vsbc.vvm v8, v4, v8, v0
# CHECK-INST: vsbc.vvm v8, v4, v8, v0
# CHECK-ENCODING: [0x57,0x04,0x44,0x48]
# CHECK-ENCODING: [0x57,0x04,0x44,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 04 44 48 <unknown>
# CHECK-UNKNOWN: 57 04 44 4a <unknown>

vsbc.vxm v8, v4, a0, v0
# CHECK-INST: vsbc.vxm v8, v4, a0, v0
# CHECK-ENCODING: [0x57,0x44,0x45,0x48]
# CHECK-ENCODING: [0x57,0x44,0x45,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 44 45 48 <unknown>
# CHECK-UNKNOWN: 57 44 45 4a <unknown>

vmsbc.vvm v8, v4, v20, v0
# CHECK-INST: vmsbc.vvm v8, v4, v20, v0
# CHECK-ENCODING: [0x57,0x04,0x4a,0x4c]
# CHECK-ENCODING: [0x57,0x04,0x4a,0x4e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 04 4a 4c <unknown>
# CHECK-UNKNOWN: 57 04 4a 4e <unknown>

vmsbc.vvm v4, v4, v20, v0
# CHECK-INST: vmsbc.vvm v4, v4, v20, v0
# CHECK-ENCODING: [0x57,0x02,0x4a,0x4c]
# CHECK-ENCODING: [0x57,0x02,0x4a,0x4e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 02 4a 4c <unknown>
# CHECK-UNKNOWN: 57 02 4a 4e <unknown>

vmsbc.vvm v8, v4, v8, v0
# CHECK-INST: vmsbc.vvm v8, v4, v8, v0
# CHECK-ENCODING: [0x57,0x04,0x44,0x4c]
# CHECK-ENCODING: [0x57,0x04,0x44,0x4e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 04 44 4c <unknown>
# CHECK-UNKNOWN: 57 04 44 4e <unknown>

vmsbc.vxm v8, v4, a0, v0
# CHECK-INST: vmsbc.vxm v8, v4, a0, v0
# CHECK-ENCODING: [0x57,0x44,0x45,0x4c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 44 45 4c <unknown>

vmsbc.vv v8, v4, v20
# CHECK-INST: vmsbc.vv v8, v4, v20
# CHECK-ENCODING: [0x57,0x04,0x4a,0x4e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 04 4a 4e <unknown>

vmsbc.vx v8, v4, a0
# CHECK-INST: vmsbc.vx v8, v4, a0
# CHECK-ENCODING: [0x57,0x44,0x45,0x4e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 44 45 4e <unknown>
Expand Down
Loading

0 comments on commit bd5ad97

Please sign in to comment.