fix style to satisfy clang-format 18.1.3

legacy/core/src/compiler/codegen/codegen_c.cpp

@@ -1,18 +1,19 @@
-/*******************************************************************************
- * Copyright 2020-2023 Intel Corporation
+/*
+ * Copyright (C) 2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *******************************************************************************/
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include "codegen_c.hpp"
 #include "../ir/viewer.hpp"
@@ -1219,9 +1220,8 @@ void c_generator_pass_t::operator()(func_t f) {
 c_generator_pass_t::c_generator_pass_t(std::ostream &source,
                                        const context_ptr &ctx, bool gen_wrapper,
                                        c_generator_optional_out_t *optional_out)
-    : source_(source), context_(ctx),
-      gen_wrapper_(gen_wrapper), pre_passes_{get_default_precodegen_passes(
-                                     ctx, gen_wrapper)},
+    : source_(source), context_(ctx), gen_wrapper_(gen_wrapper),
+      pre_passes_{get_default_precodegen_passes(ctx, gen_wrapper)},
       optional_out_(optional_out) {
   prepare_include(&source_);
   if (optional_out_) {

legacy/core/src/compiler/codegen/llvm/intrinsic_impl.cpp

@@ -1,18 +1,19 @@
-/*******************************************************************************
- * Copyright 2023-2024 Intel Corporation
+/*
+ * Copyright (C) 2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *******************************************************************************/
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #include <algorithm>
 #include <fstream>
 #include <memory>
@@ -74,7 +75,7 @@ Value *codegen_llvm_vis_t::make_int_min_max(const intrin_call_c &v, bool ismin,
 Value *codegen_llvm_vis_t::make_int_min_max(Value *v1, Value *v2, bool ismin,
                                             type_category cate) {
   // fix-me: use smax/smin for newer LLVM
-  llvm::Value *(llvm::IRBuilder<>::*ptr)(llvm::Value * LHS, llvm::Value * RHS,
+  llvm::Value *(llvm::IRBuilder<>::*ptr)(llvm::Value *LHS, llvm::Value *RHS,
                                          const llvm::Twine &Name);
   if (ismin) {
     if (cate == CATE_INT) {

legacy/core/src/compiler/ir/graph/anchor_loop_generator.cpp

@@ -1,18 +1,19 @@
-/*******************************************************************************
- * Copyright 2023 Intel Corporation
+/*
+ * Copyright (C) 2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *******************************************************************************/
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include "anchor_loop_generator.hpp"
 #include "fusible_op_utils.hpp"

legacy/core/src/compiler/ir/graph/anchor_loop_generator.hpp

@@ -1,18 +1,19 @@
-/*******************************************************************************
- * Copyright 2023 Intel Corporation
+/*
+ * Copyright (C) 2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *******************************************************************************/
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #ifndef GRAPH_BACKEND_GRAPH_COMPILER_CORE_SRC_COMPILER_IR_GRAPH_ANCHOR_LOOP_GENERATOR_HPP
 #define GRAPH_BACKEND_GRAPH_COMPILER_CORE_SRC_COMPILER_IR_GRAPH_ANCHOR_LOOP_GENERATOR_HPP
@@ -54,7 +55,7 @@ class anchor_loop_generator_t : public body_generator_base_t {
       const std::shared_ptr<fusion_anchor_t> &parent_fanchor) const;
 
   void schedule_loops(context_ptr ctx, const void *config, stmt body,
-                      std::vector<for_loop> &fors) const override{};
+                      std::vector<for_loop> &fors) const override {};
   float get_gflop() const override { return 0; }
 };
 

legacy/core/src/compiler/ir/graph/graph_map.hpp

@@ -1,18 +1,19 @@
-/*******************************************************************************
- * Copyright 2022-2023 Intel Corporation
+/*
+ * Copyright (C) 2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *******************************************************************************/
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #ifndef GRAPH_BACKEND_GRAPH_COMPILER_CORE_SRC_COMPILER_IR_GRAPH_GRAPH_MAP_HPP
 #define GRAPH_BACKEND_GRAPH_COMPILER_CORE_SRC_COMPILER_IR_GRAPH_GRAPH_MAP_HPP
@@ -26,7 +27,9 @@ namespace impl {
 namespace graph {
 namespace gc {
 
-template <typename T> struct is_vector { static constexpr bool value = false; };
+template <typename T> struct is_vector {
+  static constexpr bool value = false;
+};
 
 template <typename T, typename Alloc> struct is_vector<std::vector<T, Alloc>> {
   static constexpr bool value = true;

legacy/core/src/compiler/ir/graph/graph_op.hpp

@@ -1,18 +1,19 @@
-/*******************************************************************************
- * Copyright 2020-2023 Intel Corporation
+/*
+ * Copyright (C) 2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *******************************************************************************/
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef GRAPH_BACKEND_GRAPH_COMPILER_CORE_SRC_COMPILER_IR_GRAPH_GRAPH_OP_HPP
 #define GRAPH_BACKEND_GRAPH_COMPILER_CORE_SRC_COMPILER_IR_GRAPH_GRAPH_OP_HPP
 
@@ -48,7 +49,7 @@ class graph_op_t : public sc_op {
   void query_format(
       context_ptr ctx,
       std::vector<std::vector<format_stride_pair>> &supported_ins,
-      std::vector<std::vector<format_stride_pair>> &supported_outs) override{};
+      std::vector<std::vector<format_stride_pair>> &supported_outs) override {};
 
   // the param graph is created by upper function and passed to this function.
   // It should be an empty graph and already synced with external graph.

legacy/core/src/compiler/ir/graph/mixed_partition.cpp

@@ -1,18 +1,19 @@
-/*******************************************************************************
- * Copyright 2022-2024 Intel Corporation
+/*
+ * Copyright (C) 2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *******************************************************************************/
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include "mixed_partition.hpp"
 #include "binding_axis.hpp"
@@ -1849,8 +1850,8 @@ static bool try_merge_mixed_parti_parallel(mixed_parti_t *A, mixed_parti_t *B) {
 
   auto append_parti = (dep == parti_dep::l_dep_r) ? A : B,
        target_parti = (dep == parti_dep::l_dep_r) ? B : A;
-  SC_MODULE_INFO << "Start try_merge_mixed_parti_parallel: "
-                 << "Target: " << target_parti->func_->name_
+  SC_MODULE_INFO << "Start try_merge_mixed_parti_parallel: " << "Target: "
+                 << target_parti->func_->name_
                  << ", Append: " << append_parti->func_->name_;
 
   auto outer_loops_target = target_parti->get_outer_loops(),
@@ -4028,7 +4029,7 @@ static void
 crossover_dispatcher(const std::vector<mixed_parti_t::ptr> &parti_vec,
                      parti_merge_kind merge_kind) {
   // select merger by merge kind
-  bool (*merger)(mixed_parti_t * A, mixed_parti_t * B);
+  bool (*merger)(mixed_parti_t *A, mixed_parti_t *B);
   switch (merge_kind) {
   case parti_merge_kind::vertical: {
     merger = try_merge_mixed_parti_vertically;

legacy/core/src/compiler/ir/intrinsics.hpp

@@ -1,18 +1,19 @@
-/*******************************************************************************
- * Copyright 2020-2024 Intel Corporation
+/*
+ * Copyright (C) 2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *******************************************************************************/
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #ifndef GRAPH_BACKEND_GRAPH_COMPILER_CORE_SRC_COMPILER_IR_INTRINSICS_HPP
 #define GRAPH_BACKEND_GRAPH_COMPILER_CORE_SRC_COMPILER_IR_INTRINSICS_HPP
@@ -38,7 +39,7 @@ struct intrinsic_handler_t {
 };
 
 struct x86_intrinsic_handler_t : public intrinsic_handler_t {
-  virtual void on_initialize(intrin_call_node &node){};
+  virtual void on_initialize(intrin_call_node &node) {};
   virtual void on_initialize(low_level_intrin_node &node) = 0;
   x86_intrinsic_handler_t(const std::string &name);
   virtual ~x86_intrinsic_handler_t() = default;

legacy/core/src/compiler/ir/transform/dynamic_parallel_transform.cpp

@@ -1,18 +1,19 @@
-/*******************************************************************************
- * Copyright 2023-2024 Intel Corporation
+/*
+ * Copyright (C) 2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *******************************************************************************/
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include "dynamic_parallel_transform.hpp"
 #include <algorithm>
@@ -123,8 +124,8 @@ struct parallel_for_scope_t {
                        bool is_start, uint64_t tid_step,
                        const std::vector<expr_c> *parent_iters,
                        const expr_c &cur_iter)
-      : loop_{loop},
-        nested_level_{nested_level}, is_start_{is_start}, tid_step_{tid_step} {
+      : loop_{loop}, nested_level_{nested_level}, is_start_{is_start},
+        tid_step_{tid_step} {
     if (parent_iters) {
       iters_ = *parent_iters;
       if (cur_iter.defined()) {