DPC++ daily 2021-10-20

[SYCL] Include backend-specific header if exists (#4783)

https://www.khronos.org/registry/SYCL/specs/sycl-2020/html/sycl-2020.html#sec:headers-and-namespaces
introduces the backend specific headers "sycl/backend/<backend_name>.hpp"
CTS tests assume that if backend macro is defined (e.g. SYCL_BACKEND_OPENCL)
it is fully functional without extra includes. So the patch adds
include of the backend specific header when the backend is enabled.

The change should fix the recent massive failure of CTS tests with the error:
implicit instantiation of undefined template 'sycl::interop<sycl::backend::opencl, sycl::platform>'
Co-authored-by: Mikhail Lychkov <mikhail.lychkov@intel.com>
Co-authored-by: Mikhail Lychkov <mikhail.lychkov@intel.com>

DPC++ daily 2021-10-19

[SYCL][LIBCLC] Change __clc_size_t to unsigned (#4784)

This changes the `__clc_size_t` from a signed 64-bit int to an unsigned 64-bit int. 
The change results in the correct mangled name for `GroupAsyncCopy` built-ins. 

This is a proposed solution to issue #4502

DPC++ daily 2021-10-18

sycl-nightly/20211018

[SYCL][PI] New device information descriptors: max_global_work_groups…

DPC++ daily 2021-10-17

sycl-nightly/20211017

[NFC] Remove accidentally committed file. (#4737)

DPC++ daily 2021-10-16

[sycl-post-link][NFC] Various small refactorings (#4731)

- Replaced `static` functions and variables with usage of anonymous namespace.
- Renamed some functions.
- Applied clang-format to most of the `sycl-post-link.cpp` file.
- Removed some unnecessary includes, added some which were missing (like `<vector>`).
- Added `const` qualifier almost everywhere.
- Updated _some_ comments to use "entry point" instead of "kernel".
  Full replace requires renaming corresponding command line options,
  which should be done in sync with the driver - I would prefer to do so
  in a separate commit.

DPC++ daily 2021-10-15

Renaming esimd emu from esimd cpu (#4728)

[SYCL][ESIMD][EMU] Renaming ESIMD_CPU to ESIMD_EMU
* Directory rename
* File rename
Co-authored-by: kbobrovs <Konstantin.S.Bobrovsky@intel.com>

DPC++ daily 2021-10-14

sycl-nightly/20211014

[SYCL] Enable querying kernel's number of registers (#4665)

DPC++ daily 2021-10-13

[SYCL] Disable fallback assert for interop kernels (#4712)

Signed-off-by: Sergey Kanaev <sergey.kanaev@intel.com>

DPC++ daily 2021-10-12

[SYCL] Use device code cache when building kernel bundles (#4724)

The persistent device code cache, when enabled, is not used when
building the underlying native program in a kernel bundle. These changes
unify cache lookup with a fallback to program creation from
ProgramManager::getBuiltPIProgram with the program creation in
ProgramManager::build, ensuring that the latter also uses cached device
code. Likewise, ProgramManager::build will write the device code to the
persistent cache if it was not there already.

Signed-off-by: Steffen Larsen <steffen.larsen@intel.com>

DPC++ daily 2021-10-11

[ESIMD] Refactor esimd intrinsic mapping to BE intrinsics. (#4720)

* [ESIMD] Refactor esimd intrinsic mapping to BE intrinsics.

This patch
- makes names and parameter lists of __esimd* intrinsics match their
  @llvm.genx counterparts. The benefits are:
  * this removes the extra logical translation layer between __esimd* and
    @llvm.genx thus simplifying overall user-level esimd intrinsic translation
  * allows to reuse lots of functionality between SLM and surface memory
    accesses
- moves some of the translations and argument setting (like accessor field to
  surface index, setting scale) from LowerESIMD.cpp to the ESIMD headers, which
  simplifies code base.
- for all memory intrinsics moves host and device implementations to the same
  intrinsic function prototype separating them via __SYCL_DEVICE_ONLY__ macro
  thus avoiding duplication of the prototypes
- removes certain redundant __esimd* intrinsics, such as SLM memory accesses
  (which are normal surface accesses with special surface index 254), and
  __esimd_reduced_fmax,... which have the same functionality as usual fmax,...

This is also a preparatory step for fixing SLM memory accesses (revising vector
lengths, element types restirictions)

Signed-off-by: Konstantin S Bobrovsky <konstantin.s.bobrovsky@intel.com>