oneAPI DPC++ Compiler dependencies

This release contains OpenCL RT for Intel CPU and FPGA emulator used for oneAPI DPC++ Compiler and runtime validation
Please, see the runtime installation guide here.

DPC++ daily 2021-09-29

[SYCL] Fix overwriting insert to sub_group_mask (#4656)

Make sure that old value is cleared when inserted bits ovewrite whole
mask.

DPC++ daily 2021-09-28

[sycl-post-link] Fix out-of-bound access in the tool (#4638)

Added an early exit into a loop over results of
`SPIRKernelParamOptInfoAnalysis` pass to avoid accessing an empty
`llvm::BitVector` at index 0.

DPC++ daily 2021-09-25

[SYCL] Disallow sycl_kernel attribute on host (#4618)

This is essentially a revert of PR #2186, as the supposed
optimization did not materialize. I have removed the
functionality added in that PR, while keeping the code
cleanups.

DPC++ daily 2021-09-24

[SYCL] Make device ids unique per backend (#4247)

* [SYCL] Make device ids unique per backend

We decided to make device id numbers unique per backend.
Also, by adding the device_type into each device prefix listing in sycl-ls,
the user can easily set SYCL_DEVICE_FILTER correctly.
Future work: refactor devices and platforms cache to optimize the device retrieval.

Signed-off-by: Byoungro So <byoungro.so@intel.com>
Co-authored-by: Alexey Bader <alexey.bader@intel.com>
Co-authored-by: Romanov Vlad <vlad.romanov@intel.com>

DPC++ daily 2021-09-23

[clang-offload-extract] Ignore zero padding in .tgting section (#4622)

This patch changes clang-offload-extract to ignore zero padding
when reading .tgtimg section contents. Such padding can be added
to the section by (msvc) linker.

Signed-off-by: Sergey Dmitriev <serguei.n.dmitriev@intel.com>

DPC++ daily 2021-09-22

sycl-nightly/20210922

[SYCL][L0] Make sure that we only query/sync host-visible events from…

DPC++ daily 2021-09-21

sycl-nightly/20210921

[ESIMD] Replace mask_type_t with simd_mask to represent Gen predicate…

DPC++ daily 2021-09-20

[SYCL] Fix zero dimension accessors on FPGA in AOT mode (#4458)

Zero dimension accessors aren't working on FPGA with atomic data.
When aot compiling for FPGA we use address space
global_device_space instead of just global_space. This seems to be
confusing the specialization for the zero dimension accessor. Not
overspecifying the address space fixes the problem with no other
change in functionality.

Signed-off-by: Chris Perkins <chris.perkins@intel.com>

DPC++ daily 2021-09-19

[SYCL] Implement sub-group mask extension  (#4481)

The specification is available under https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SubGroupMask/SubGroupMask.asciidoc

Complementary test changes are available under intel/llvm-test-suite#441, intel/llvm-test-suite#462