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Naming definition #160
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Naming definition #160
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mkorbel1
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Jan 31, 2025
mkorbel1
reviewed
Jan 31, 2025
test/arithmetic/floating_point/floating_point_multiplier_test.dart
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mkorbel1
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Description & Motivation
Adding definitionName entries for components so that Verilog has fewer unique modules generated and names
are more meaningful.
Migrate to ROHD 0.6.1
Added NativeMultiplier wrapper for use in generating Verilog to use native multipliers.
Moved optional clocking into base Multiplier class.
Variable width optional output for FP Multiplier,
Related Issue(s)
None.
Testing
Inspected Verilog output of arithmetic blocks, ran logic synthesis to make sure the naming conventions were good.
Exhaustive tests for NativeMultiplier as well as FP Multiplier optional wide output.
Backwards-compatibility
No.
Documentation
API documentation changes inline with code for new components and the new optional inputs for FP Mult.