fix constant collapsing, fix #159

lib/src/synthesizers/systemverilog.dart

@@ -201,7 +201,7 @@ class _SystemVerilogSynthesisResult extends SynthesisResult {
       _verilogInternalNets(),
       _verilogAssignments(),
       _verilogSubModuleInstantiations(moduleToInstanceTypeMap),
-    ].join('\n');
+    ].where((element) => element.isNotEmpty).join('\n');
   }
 
   String _verilogPorts() {
@@ -581,6 +581,8 @@ class _SynthLogic {
       throw Exception(
           'This _SynthLogic ($this) cannot be renamed to $constant.');
     }
+    _mergedNameSynthLogic
+        ?.mergeConst(constant); // in case we're changing direction of merge
     _mergedNameSynthLogic = null;
     _mergedConst = constant;
     _needsDeclaration = false;

lib/src/utilities/simcompare.dart

@@ -117,6 +117,7 @@ class SimCompare {
     bool dumpWaves = false,
     Map<String, int> signalToWidthMap = const {},
     List<String> iverilogExtraArgs = const [],
+    bool allowWarnings = false,
   }) {
     String signalDeclaration(String signalName) {
       if (signalToWidthMap.containsKey(signalName)) {
@@ -172,9 +173,13 @@ class SimCompare {
         ['-g2012', tmpTestFile, '-o', tmpOutput] + iverilogExtraArgs);
     bool printIfContentsAndCheckError(dynamic output) {
       if (output.toString().isNotEmpty) print(output);
-      return output
-          .toString()
-          .contains(RegExp('error|unable|warning', caseSensitive: false));
+      return output.toString().contains(RegExp(
+          [
+            'error',
+            'unable',
+            if (!allowWarnings) 'warning',
+          ].join('|'),
+          caseSensitive: false));
     }
 
     if (printIfContentsAndCheckError(compileResult.stdout)) return false;

test/assignment_test.dart

@@ -0,0 +1,48 @@
+/// Copyright (C) 2021 Intel Corporation
+/// SPDX-License-Identifier: BSD-3-Clause
+///
+/// assignment_test.dart
+/// Unit tests for assignment-specific issues.
+///
+/// 2022 September 19
+/// Author: Max Korbel <max.korbel@intel.com>
+///
+
+import 'package:rohd/rohd.dart';
+import 'package:test/test.dart';
+import 'package:rohd/src/utilities/simcompare.dart';
+
+class ExampleModule extends Module {
+  ExampleModule() {
+    final out = addOutput('out');
+    final val = Logic(name: 'val');
+    val <= Const(1);
+
+    Combinational([
+      out < val,
+    ]);
+  }
+
+  Logic get out => output('out');
+}
+
+void main() {
+  // From https://github.com/intel/rohd/issues/159
+  // Thank you to @chykon for reporting!
+  test('const comb assignment', () async {
+    final exampleModule = ExampleModule();
+    await exampleModule.build();
+
+    var vectors = [
+      Vector({}, {'out': 1}),
+    ];
+    await SimCompare.checkFunctionalVector(exampleModule, vectors);
+    var simResult = SimCompare.iverilogVector(
+      exampleModule.generateSynth(),
+      exampleModule.runtimeType.toString(),
+      vectors,
+      allowWarnings: true, // since always_comb has no sensitivities
+    );
+    expect(simResult, equals(true));
+  });
+}