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RTL to have one array-array assignment instead of bit blasted assignments #487

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merged 6 commits into from
Jun 13, 2024

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sshankar4
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Description & Motivation

For compatibility purposes, ROHD currently does per-element assignments between arrays. A common case of assignment between two entire arrays of the same dimensions makes many more lines than is necessary. This makes the generated SV more verbose than it needs to be.

Related Issue(s)

#482

Testing

Added new tests

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Documentation is not required for this change.

@sshankar4 sshankar4 changed the title RTL to have one array-array assignment instead of bit blasted assignments when RTL to have one array-array assignment instead of bit blasted assignments Jun 6, 2024
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@mkorbel1 mkorbel1 merged commit 9cad7eb into intel:main Jun 13, 2024
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@sshankar4 sshankar4 deleted the shankar_rtl branch June 13, 2024 20:30
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Make full array assignments compressed to 1 line (or in-lined) in generated SystemVerilog
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