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[vmvx] Relax requirement on fptosi lowering #11553

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merged 4 commits into from
Dec 14, 2022
Merged

[vmvx] Relax requirement on fptosi lowering #11553

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117d10f
[vmvx] Relax requirement on fptosi lowering
jpienaar Dec 14, 2022
2debfbf
Use getIn instead of adaptor.getOperands()[0]
jpienaar Dec 14, 2022
41185bf
Use getIn instead of adaptor.getOperands()[0] missed case
jpienaar Dec 14, 2022
e749a5a
Formatting
jpienaar Dec 14, 2022
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14 changes: 8 additions & 6 deletions compiler/src/iree/compiler/Dialect/VM/Conversion/StandardToVM/ConvertStandardToVM.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -926,11 +926,13 @@ class FPToSIOpConversion : public OpConversionPattern<arith::FPToSIOp> {
ConversionPatternRewriter &rewriter) const override {
auto srcType = srcOp.getIn().getType();
auto dstType = srcOp.getResult().getType();
auto resultType = getTypeConverter()->convertType(dstType);
if (srcType.isF32()) {
if (dstType.isSignlessInteger(32) || dstType.isSignedInteger(32)) {
auto resultType = getTypeConverter()->convertType(dstType);
rewriter.replaceOpWithNewOp<IREE::VM::CastF32SI32Op>(
srcOp, resultType, adaptor.getOperands()[0]);
// This uses the resultType rather than dstType as any truncation
// required will be handled via interpretation by consumer.
if (resultType.isSignlessInteger(32) || resultType.isSignedInteger(32)) {
rewriter.replaceOpWithNewOp<IREE::VM::CastF32SI32Op>(srcOp, resultType,
adaptor.getIn());
return success();
}
}
Expand All @@ -948,8 +950,8 @@ class FPToUIOpConversion : public OpConversionPattern<arith::FPToUIOp> {
auto resultType = getTypeConverter()->convertType(dstType);
if (srcType.isF32()) {
if (dstType.isSignlessInteger(32) || dstType.isUnsignedInteger(32)) {
rewriter.replaceOpWithNewOp<IREE::VM::CastF32UI32Op>(
srcOp, resultType, adaptor.getOperands()[0]);
rewriter.replaceOpWithNewOp<IREE::VM::CastF32UI32Op>(srcOp, resultType,
adaptor.getIn());
return success();
}
}
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2 changes: 1 addition & 1 deletion compiler/src/iree/compiler/Dialect/VM/Conversion/StandardToVM/test/conversion_ops.mlir
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Expand Up @@ -77,7 +77,7 @@ module @my_module {
module @t006_fptosi_fp32_i8 {
module @my_module {
func.func @my_fn(%arg0 : f32) -> (i8) {
// expected-error@+1 {{failed to legalize}}
// CHECK: vm.cast.f32.si32 %[[ARG0]] : f32 -> i32
%1 = arith.fptosi %arg0 : f32 to i8
return %1 : i8
Comment on lines +80 to 82
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Are there other IRs that truncate i32 to i8? If so, should we check it as well?

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We checked the integer ones yesterday (8a3d270). At least for those individually the result wrt llvm and vmvx was the same.

}
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