A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog and a little VHDL.
See report.pdf for further information.
See src in Vivado.
- release/top.bit is for normal use on Basys 3 Artix-7 FPGA.
- release/top.bin is for using SPI Flash memory to enable plug and play.