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TO DO
jacgoudsmit edited this page Nov 7, 2014
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This is a list of items that have been, and/or will be implemented in the Github repo. The list is in random order. Click on the items for more information.
- (Cluso99) Add comments
- (Pik33) Support for DE1-SOC
- Modify Verilog to allow using Altera ModelSim
- (Seairth) Update DE0 pin mappings for compatibility with breakout board
- (Jac Goudsmit) Adapt pin mappings for compatibility with QuickStart (may need to design a board)
- (Pik33) Use port B to control external RAM
- (Various) Implement port B as it was intended, with or without physical pins
- (Jac Goudsmit) Combine Xilinx targets into one project
- (Jac Goudsmit) Combine Xilinx and Altera source code; all Verilog in one directory
- (Cluso99) AUGDS instructions to extend instructions to 16 bits
- (Cluso99) Reduced number of cogs
- (Jac Goudsmit) Enable incompatible features by writing to CNT and VCFG
- (Seairth) Add timing analysis files
- (6581) Add pinout image generator tool
- Add weak pullups to pin specifications
Under consideration (i.e. these may be added later):
- (Cluso99) Break 2K cog ram barrier (Potential compatibility problems)
- (Rogloh) Stack functionality: (Potential compatibility problems)
- (Porcupine) Support for MiST board (Cyclone III) (Requires Quartus 13.1 instead of 14.0; also no-one has this hardware)
- (Cluso99) 48K hub RAM and remapped ROM (Potential compatibility problems)
- (Pik33) SRAM VGA mode (Hardware-specific)
- (Overclocked) LCD display (Hardware-specific to Microblaze)
- (Prof_Braino) Regression suite based on PropForth (Proposed)
- (Willy Ekerslyke) Implement MUL/MULS using hardware multiplier (Possibly Altera-specific)
- (Cluso99) Reduced number of video generators (Not enough information available at this time)
- (ozpropdev) Running 5 P1V's one one DE2-115 (Hardware-specific to DE2-115)
Done or almost done:
- (Cluso99) Unscrambled ROM (Done in Altera branch)
- (Jac Goudsmit) Combine Altera targets into one project, using macros/parameters to enable features (Done in Altera branch)
- (6581, Jac Goudsmit) Fix BeMicro CV LEDs (order of LEDs and inverted electronics) (Done)
- (Magnus Karlsson) Ported to Pipistrello (Xilinx Spartan-6) (Done)
- (Andy Silverman) Ported to Digilent Nexys4 (Xilinx Artix-7) (Done)
- (Andy Silverman) Fixed bug in PLL simulation code (Done)
- (Seairth, others) Convert AHDL to Verilog (Done in Altera branch)
- (Jac Goudsmit) Resize RAM/ROM as needed and (auto-)cherry-pick ROM images (Done in Altera branch, however, current implementation can't increase RAM on DE0 because it runs out of M9K blocks)