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Merged main:0261ce9e17bd into amd-gfx:ccce20cae2a7
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Local branch amd-gfx ccce20c Merged main:f99b4f5241a3 into amd-gfx:21e62802cf23
Remote branch main 0261ce9 [X86] Add ExeDomain = SSEPackedSingle to cvtss2sd and cvtsd2ss instrutions.
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Sw authored and Sw committed Dec 13, 2020
2 parents ccce20c + 0261ce9 commit 661043e
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Showing 6 changed files with 235 additions and 146 deletions.
8 changes: 8 additions & 0 deletions llvm/lib/Analysis/AssumptionCache.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -115,6 +115,14 @@ findAffectedValues(CallInst *CI,
AddAffectedFromEq(A);
AddAffectedFromEq(B);
}

Value *X;
// Handle (A + C1) u< C2, which is the canonical form of A > C3 && A < C4,
// and recognized by LVI at least.
if (Pred == ICmpInst::ICMP_ULT &&
match(A, m_Add(m_Value(X), m_ConstantInt())) &&
match(B, m_ConstantInt()))
AddAffected(X);
}
}

Expand Down
9 changes: 2 additions & 7 deletions llvm/lib/Target/X86/X86InstrAVX512.td
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Original file line number Diff line number Diff line change
Expand Up @@ -7569,7 +7569,7 @@ multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr,
SDNode OpNode, SDNode OpNodeRnd,
X86FoldableSchedWrite sched,
X86VectorVTInfo _src, X86VectorVTInfo _dst> {
let Predicates = [HasAVX512] in {
let Predicates = [HasAVX512], ExeDomain = SSEPackedSingle in {
defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode, sched>,
avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
OpNodeRnd, sched>, VEX_W, EVEX_CD8<64, CD8VT1>, XD;
Expand All @@ -7580,7 +7580,7 @@ multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr,
SDNode OpNode, SDNode OpNodeSAE,
X86FoldableSchedWrite sched,
X86VectorVTInfo _src, X86VectorVTInfo _dst> {
let Predicates = [HasAVX512] in {
let Predicates = [HasAVX512], ExeDomain = SSEPackedSingle in {
defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode, sched>,
avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeSAE, sched>,
EVEX_CD8<32, CD8VT1>, XS;
Expand Down Expand Up @@ -11914,11 +11914,6 @@ defm VPDPBUSDS : VNNI_common<0x51, "vpdpbusds", X86Vpdpbusds, SchedWriteVecIMul
defm VPDPWSSD : VNNI_common<0x52, "vpdpwssd", X86Vpdpwssd, SchedWriteVecIMul, 1>;
defm VPDPWSSDS : VNNI_common<0x53, "vpdpwssds", X86Vpdpwssds, SchedWriteVecIMul, 1>;

def X86vpmaddwd_su : PatFrag<(ops node:$lhs, node:$rhs),
(X86vpmaddwd node:$lhs, node:$rhs), [{
return N->hasOneUse();
}]>;

// Patterns to match VPDPWSSD from existing instructions/intrinsics.
let Predicates = [HasVNNI] in {
def : Pat<(v16i32 (add VR512:$src1,
Expand Down
34 changes: 28 additions & 6 deletions llvm/lib/Target/X86/X86InstrSSE.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1242,7 +1242,8 @@ def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
/// SSE 2 Only

// Convert scalar double to scalar single
let isCodeGenOnly = 1, hasSideEffects = 0, Predicates = [UseAVX] in {
let isCodeGenOnly = 1, hasSideEffects = 0, Predicates = [UseAVX],
ExeDomain = SSEPackedSingle in {
def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
(ins FR32:$src1, FR64:$src2),
"cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
Expand All @@ -1260,7 +1261,7 @@ def : Pat<(f32 (any_fpround FR64:$src)),
(VCVTSD2SSrr (f32 (IMPLICIT_DEF)), FR64:$src)>,
Requires<[UseAVX]>;

let isCodeGenOnly = 1 in {
let isCodeGenOnly = 1, ExeDomain = SSEPackedSingle in {
def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
"cvtsd2ss\t{$src, $dst|$dst, $src}",
[(set FR32:$dst, (any_fpround FR64:$src))]>,
Expand All @@ -1272,7 +1273,7 @@ def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
Sched<[WriteCvtSD2SS.Folded]>, SIMD_EXC;
}

let Uses = [MXCSR], mayRaiseFPException = 1 in {
let Uses = [MXCSR], mayRaiseFPException = 1, ExeDomain = SSEPackedSingle in {
def VCVTSD2SSrr_Int: I<0x5A, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
"vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Expand Down Expand Up @@ -1306,7 +1307,7 @@ def CVTSD2SSrm_Int: I<0x5A, MRMSrcMem,

// Convert scalar single to scalar double
// SSE2 instructions with XS prefix
let isCodeGenOnly = 1, hasSideEffects = 0 in {
let isCodeGenOnly = 1, hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
(ins FR64:$src1, FR32:$src2),
"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
Expand All @@ -1326,7 +1327,7 @@ def : Pat<(f64 (any_fpextend FR32:$src)),
def : Pat<(any_fpextend (loadf32 addr:$src)),
(VCVTSS2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX, OptForSize]>;

let isCodeGenOnly = 1 in {
let isCodeGenOnly = 1, ExeDomain = SSEPackedSingle in {
def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
"cvtss2sd\t{$src, $dst|$dst, $src}",
[(set FR64:$dst, (any_fpextend FR32:$src))]>,
Expand All @@ -1338,7 +1339,8 @@ def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
Sched<[WriteCvtSS2SD.Folded]>, SIMD_EXC;
} // isCodeGenOnly = 1

let hasSideEffects = 0, Uses = [MXCSR], mayRaiseFPException = 1 in {
let hasSideEffects = 0, Uses = [MXCSR], mayRaiseFPException = 1,
ExeDomain = SSEPackedSingle in {
def VCVTSS2SDrr_Int: I<0x5A, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Expand Down Expand Up @@ -7206,6 +7208,26 @@ defm VPDPBUSDS : avx_vnni_rm<0x51, "vpdpbusds", X86Vpdpbusds, 0>, ExplicitVEXPr
defm VPDPWSSD : avx_vnni_rm<0x52, "vpdpwssd", X86Vpdpwssd, 1>, ExplicitVEXPrefix;
defm VPDPWSSDS : avx_vnni_rm<0x53, "vpdpwssds", X86Vpdpwssds, 1>, ExplicitVEXPrefix;

def X86vpmaddwd_su : PatFrag<(ops node:$lhs, node:$rhs),
(X86vpmaddwd node:$lhs, node:$rhs), [{
return N->hasOneUse();
}]>;

let Predicates = [HasAVXVNNI, NoVLX_Or_NoVNNI] in {
def : Pat<(v8i32 (add VR256:$src1,
(X86vpmaddwd_su VR256:$src2, VR256:$src3))),
(VPDPWSSDYrr VR256:$src1, VR256:$src2, VR256:$src3)>;
def : Pat<(v8i32 (add VR256:$src1,
(X86vpmaddwd_su VR256:$src2, (load addr:$src3)))),
(VPDPWSSDYrm VR256:$src1, VR256:$src2, addr:$src3)>;
def : Pat<(v4i32 (add VR128:$src1,
(X86vpmaddwd_su VR128:$src2, VR128:$src3))),
(VPDPWSSDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
def : Pat<(v4i32 (add VR128:$src1,
(X86vpmaddwd_su VR128:$src2, (load addr:$src3)))),
(VPDPWSSDrm VR128:$src1, VR128:$src2, addr:$src3)>;
}

//===----------------------------------------------------------------------===//
// VPERMIL - Permute Single and Double Floating-Point Values
//
Expand Down
130 changes: 0 additions & 130 deletions llvm/test/CodeGen/X86/avx512vnni.ll
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Original file line number Diff line number Diff line change
@@ -1,134 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=CHECK

define <4 x i32> @test_pmaddwd_v8i16_add_v4i32(<4 x i32> %a0, <8 x i16> %a1, <8 x i16> %a2) {
; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: retq
%1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
%2 = add <4 x i32> %1, %a0
ret <4 x i32> %2
}

define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute(<4 x i32> %a0, <8 x i16> %a1, <8 x i16> %a2) {
; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_commute:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: retq
%1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
%2 = add <4 x i32> %a0, %1
ret <4 x i32> %2
}

define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_load1(<4 x i32> %a0, <8 x i16>* %p1, <8 x i16> %a2) {
; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_load1:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
; CHECK-NEXT: retq
%a1 = load <8 x i16>, <8 x i16>* %p1
%1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
%2 = add <4 x i32> %1, %a0
ret <4 x i32> %2
}

define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_load2(<4 x i32> %a0, <8 x i16> %a1, <8 x i16>* %p2) {
; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_load2:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
; CHECK-NEXT: retq
%a2 = load <8 x i16>, <8 x i16>* %p2
%1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
%2 = add <4 x i32> %1, %a0
ret <4 x i32> %2
}

define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute_load1(<4 x i32> %a0, <8 x i16>* %p1, <8 x i16> %a2) {
; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_commute_load1:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
; CHECK-NEXT: retq
%a1 = load <8 x i16>, <8 x i16>* %p1
%1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
%2 = add <4 x i32> %a0, %1
ret <4 x i32> %2
}

define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute_load2(<4 x i32> %a0, <8 x i16> %a1, <8 x i16>* %p2) {
; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_commute_load2:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
; CHECK-NEXT: retq
%a2 = load <8 x i16>, <8 x i16>* %p2
%1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
%2 = add <4 x i32> %a0, %1
ret <4 x i32> %2
}

define <8 x i32> @test_pmaddwd_v16i16_add_v8i32(<8 x i32> %a0, <16 x i16> %a1, <16 x i16> %a2) {
; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: retq
%1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
%2 = add <8 x i32> %1, %a0
ret <8 x i32> %2
}

define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute(<8 x i32> %a0, <16 x i16> %a1, <16 x i16> %a2) {
; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_commute:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: retq
%1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
%2 = add <8 x i32> %a0, %1
ret <8 x i32> %2
}

define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_load1(<8 x i32> %a0, <16 x i16>* %p1, <16 x i16> %a2) {
; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_load1:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
; CHECK-NEXT: retq
%a1 = load <16 x i16>, <16 x i16>* %p1
%1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
%2 = add <8 x i32> %1, %a0
ret <8 x i32> %2
}

define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_load2(<8 x i32> %a0, <16 x i16> %a1, <16 x i16>* %p2) {
; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_load2:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
; CHECK-NEXT: retq
%a2 = load <16 x i16>, <16 x i16>* %p2
%1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
%2 = add <8 x i32> %1, %a0
ret <8 x i32> %2
}

define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute_load1(<8 x i32> %a0, <16 x i16>* %p1, <16 x i16> %a2) {
; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_commute_load1:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
; CHECK-NEXT: retq
%a1 = load <16 x i16>, <16 x i16>* %p1
%1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
%2 = add <8 x i32> %a0, %1
ret <8 x i32> %2
}

define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute_load2(<8 x i32> %a0, <16 x i16> %a1, <16 x i16>* %p2) {
; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_commute_load2:
; CHECK: # %bb.0:
; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
; CHECK-NEXT: retq
%a2 = load <16 x i16>, <16 x i16>* %p2
%1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
%2 = add <8 x i32> %a0, %1
ret <8 x i32> %2
}

define <16 x i32> @test_pmaddwd_v32i16_add_v16i32(<16 x i32> %a0, <32 x i16> %a1, <32 x i16> %a2) {
; CHECK-LABEL: test_pmaddwd_v32i16_add_v16i32:
; CHECK: # %bb.0:
Expand Down Expand Up @@ -193,6 +65,4 @@ define <16 x i32> @test_pmaddwd_v32i16_add_v16i32_commute_load2(<16 x i32> %a0,
ret <16 x i32> %2
}

declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>)
declare <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16>, <16 x i16>)
declare <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16>, <32 x i16>)
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