Merged master:dbae3d50f114 into amd-gfx:318f34c7ff2a

Local branch amd-gfx 318f34c Merged master:8cc49bec2e06 into amd-gfx:7c4e68106766
Remote branch master dbae3d5 [MLIR] Support walks over regions and blocks

clang/tools/clang-format/CMakeLists.txt

@@ -7,7 +7,6 @@ add_clang_tool(clang-format
 set(CLANG_FORMAT_LIB_DEPS
   clangBasic
   clangFormat
-  clangFrontend
   clangRewrite
   clangToolingCore
   )

clang/tools/clang-format/ClangFormat.cpp

@@ -18,7 +18,6 @@
 #include "clang/Basic/SourceManager.h"
 #include "clang/Basic/Version.h"
 #include "clang/Format/Format.h"
-#include "clang/Frontend/TextDiagnosticPrinter.h"
 #include "clang/Rewrite/Core/Rewriter.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FileSystem.h"
@@ -424,11 +423,9 @@ static bool format(StringRef FileName) {
     IntrusiveRefCntPtr<llvm::vfs::InMemoryFileSystem> InMemoryFileSystem(
         new llvm::vfs::InMemoryFileSystem);
     FileManager Files(FileSystemOptions(), InMemoryFileSystem);
-    IntrusiveRefCntPtr<DiagnosticOptions> DiagOpts(new DiagnosticOptions());
-    TextDiagnosticPrinter DiagnosticsConsumer(errs(), &*DiagOpts);
     DiagnosticsEngine Diagnostics(
-        IntrusiveRefCntPtr<DiagnosticIDs>(new DiagnosticIDs), &*DiagOpts,
-        &DiagnosticsConsumer, false);
+        IntrusiveRefCntPtr<DiagnosticIDs>(new DiagnosticIDs),
+        new DiagnosticOptions);
     SourceManager Sources(Diagnostics, Files);
     FileID ID = createInMemoryFile(AssumedFileName, Code.get(), Sources, Files,
                                    InMemoryFileSystem.get());

flang/lib/Semantics/check-acc-structure.cpp

@@ -121,6 +121,19 @@ class NoBranchingEnforce {
   llvm::acc::Directive currentDirective_;
 };
 
+bool AccStructureChecker::CheckAllowedModifier(llvm::acc::Clause clause) {
+  if (GetContext().directive == llvm::acc::ACCD_enter_data ||
+      GetContext().directive == llvm::acc::ACCD_exit_data) {
+    context_.Say(GetContext().clauseSource,
+        "Modifier is not allowed for the %s clause "
+        "on the %s directive"_err_en_US,
+        parser::ToUpperCaseLetters(getClauseName(clause).str()),
+        ContextDirectiveAsFortran());
+    return true;
+  }
+  return false;
+}
+
 void AccStructureChecker::Enter(const parser::AccClause &x) {
   SetContextClause(x);
 }
@@ -375,6 +388,8 @@ void AccStructureChecker::Enter(const parser::AccClause::Copyin &c) {
   const auto &modifierClause{c.v};
   if (const auto &modifier{
           std::get<std::optional<parser::AccDataModifier>>(modifierClause.t)}) {
+    if (CheckAllowedModifier(llvm::acc::Clause::ACCC_copyin))
+      return;
     if (modifier->v != parser::AccDataModifier::Modifier::ReadOnly) {
       context_.Say(GetContext().clauseSource,
           "Only the READONLY modifier is allowed for the %s clause "
@@ -392,6 +407,8 @@ void AccStructureChecker::Enter(const parser::AccClause::Copyout &c) {
   const auto &modifierClause{c.v};
   if (const auto &modifier{
           std::get<std::optional<parser::AccDataModifier>>(modifierClause.t)}) {
+    if (CheckAllowedModifier(llvm::acc::Clause::ACCC_copyout))
+      return;
     if (modifier->v != parser::AccDataModifier::Modifier::Zero) {
       context_.Say(GetContext().clauseSource,
           "Only the ZERO modifier is allowed for the %s clause "

flang/lib/Semantics/check-acc-structure.h

@@ -115,6 +115,8 @@ class AccStructureChecker
       const llvm::acc::Directive directive,
       const parser::CharBlock &directiveSource) const;
 
+  bool CheckAllowedModifier(llvm::acc::Clause clause);
+
   llvm::StringRef getClauseName(llvm::acc::Clause clause) override;
   llvm::StringRef getDirectiveName(llvm::acc::Directive directive) override;
 };

flang/test/Semantics/acc-clause-validity.f90

@@ -45,9 +45,12 @@ program openacc_clause_validity
   !ERROR: At least one of ATTACH, COPYIN, CREATE clause must appear on the ENTER DATA directive
   !$acc enter data
 
-  !ERROR: Only the READONLY modifier is allowed for the COPYIN clause on the ENTER DATA directive
+  !ERROR: Modifier is not allowed for the COPYIN clause on the ENTER DATA directive
   !$acc enter data copyin(zero: i)
 
+  !ERROR: Modifier is not allowed for the COPYOUT clause on the EXIT DATA directive
+  !$acc exit data copyout(zero: i)
+
   !ERROR: Only the ZERO modifier is allowed for the CREATE clause on the ENTER DATA directive
   !$acc enter data create(readonly: i)
 

libcxx/docs/TestingLibcxx.rst

@@ -187,7 +187,7 @@ few requirements to the test suite. Here's some stuff you should know:
 - All tests are run in a temporary directory that is unique to that test and
   cleaned up after the test is done.
 - When a test needs data files as inputs, these data files can be saved in the
-  repository (when reasonable) and referrenced by the test as
+  repository (when reasonable) and referenced by the test as
   ``// FILE_DEPENDENCIES: <path-to-dependencies>``. Copies of these files or
   directories will be made available to the test in the temporary directory
   where it is run.

libcxx/utils/libcxx/test/config.py

@@ -266,6 +266,21 @@ def configure_features(self):
             self.config.available_features.add('libcxx_gdb')
             self.cxx.libcxx_gdb = libcxx_gdb
 
+        target_triple = getattr(self.config, 'target_triple', None)
+        if target_triple:
+            if re.match(r'^x86_64.*-apple', target_triple):
+                self.config.available_features.add('x86_64-apple')
+            if re.match(r'^x86_64.*-linux', target_triple):
+                self.config.available_features.add('x86_64-linux')
+            if re.match(r'^i.86.*', target_triple):
+                self.config.available_features.add('target-x86')
+            elif re.match(r'^x86_64.*', target_triple):
+                self.config.available_features.add('target-x86_64')
+            elif re.match(r'^aarch64.*', target_triple):
+                self.config.available_features.add('target-aarch64')
+            elif re.match(r'^arm.*', target_triple):
+                self.config.available_features.add('target-arm')
+
     def configure_compile_flags(self):
         self.configure_default_compile_flags()
         # Configure extra flags

libunwind/test/libunwind/test/config.py

@@ -43,6 +43,9 @@ def configure_compile_flags(self):
         # Stack unwinding tests need unwinding tables and these are not
         # generated by default on all Targets.
         self.cxx.compile_flags += ['-funwind-tables']
+        # Make symbols available in the tests.
+        if 'linux' in self.config.target_triple:
+            self.cxx.link_flags += ['-Wl,--export-dynamic']
         if not self.get_lit_bool('enable_threads', True):
             self.cxx.compile_flags += ['-D_LIBUNWIND_HAS_NO_THREADS']
             self.config.available_features.add('libunwind-no-threads')

libunwind/test/lit.site.cfg.in

@@ -44,10 +44,6 @@ config.test_source_root = os.path.join(config.libunwind_src_root, 'test')
 # Allow expanding substitutions that are based on other substitutions
 config.recursiveExpansionLimit = 10
 
-# Make symbols available in the tests.
-config.test_compiler_flags += " -funwind-tables "
-config.test_linker_flags += " -Wl,--export-dynamic "
-
 # Infer the test_exec_root from the build directory.
 config.test_exec_root = os.path.join(config.libunwind_obj_root, 'test')
 

llvm/include/llvm/Support/TypeSize.h

@@ -206,25 +206,6 @@ class TypeSize : public PolySize<uint64_t> {
   uint64_t getFixedSize() const { return getFixedValue(); }
   uint64_t getKnownMinSize() const { return getKnownMinValue(); }
 
-  friend bool operator<(const TypeSize &LHS, const TypeSize &RHS) {
-    assert(LHS.IsScalable == RHS.IsScalable &&
-           "Ordering comparison of scalable and fixed types");
-
-    return LHS.MinVal < RHS.MinVal;
-  }
-
-  friend bool operator>(const TypeSize &LHS, const TypeSize &RHS) {
-    return RHS < LHS;
-  }
-
-  friend bool operator<=(const TypeSize &LHS, const TypeSize &RHS) {
-    return !(RHS < LHS);
-  }
-
-  friend bool operator>=(const TypeSize &LHS, const TypeSize& RHS) {
-    return !(LHS < RHS);
-  }
-
   TypeSize &operator-=(TypeSize RHS) {
     assert(IsScalable == RHS.IsScalable &&
            "Subtraction using mixed scalable and fixed types");

llvm/lib/Target/VE/VEInstrInfo.td

@@ -205,6 +205,12 @@ def mimm : Operand<i32>, PatLeaf<(imm), [{
   let PrintMethod = "printMImmOperand";
 }
 
+// zerofp - Generic fp immediate zero value.
+def zerofp : Operand<i32>, PatLeaf<(fpimm), [{
+    return getFpImmVal(N) == 0; }]> {
+  let ParserMatchClass = ZeroAsmOperand;
+}
+
 // simm7fp - Generic fp immediate value.
 def simm7fp : Operand<i32>, PatLeaf<(fpimm), [{
     return isInt<7>(getFpImmVal(N));
@@ -827,10 +833,17 @@ multiclass BCRbpfm<string opcStr, string cmpStr, bits<8> opc, dag cond> {
               !strconcat(opcStr, ".t ", cmpStr, "$imm32")>;
 }
 multiclass BCRm<string opcStr, string opcStrAt, string opcStrAf, bits<8> opc,
-               RegisterClass RC, Operand immOp> {
+               RegisterClass RC, Operand immOp, Operand zeroOp> {
   defm rr : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, RC:$sy, RC:$sz)>;
   let cy = 0 in
-  defm ir : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, immOp:$sy, RC:$sz)>;
+  defm ir : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, immOp:$sy,
+                                                    RC:$sz)>;
+  let cz = 0 in
+  defm rz : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, RC:$sy,
+                                                    zeroOp:$sz)>;
+  let cy = 0, cz = 0 in
+  defm iz : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, immOp:$sy,
+                                                    zeroOp:$sz)>;
   let cy = 0, sy = 0, cz = 0, sz = 0, cf = 15 /* AT */, isBarrier = 1 in
   defm a : BCRbpfm<opcStrAt, "", opc, (ins)>;
   let cy = 0, sy = 0, cz = 0, sz = 0, cf = 0 /* AF */ in
@@ -1409,13 +1422,13 @@ defm BCFS : BCm<"b${cond}.s", "b.s", "baf.s", 0x1C, F32, simm7fp>;
 
 // Section 8.8.4 - BCR (Branch on Condition Relative)
 let cx = 0, cx2 = 0 in
-defm BRCFL : BCRm<"br${cf}.l", "br.l", "braf.l", 0x18, I64, simm7>;
+defm BRCFL : BCRm<"br${cf}.l", "br.l", "braf.l", 0x18, I64, simm7, zero>;
 let cx = 1, cx2 = 0 in
-defm BRCFW : BCRm<"br${cf}.w", "br.w", "braf.w", 0x18, I32, simm7>;
+defm BRCFW : BCRm<"br${cf}.w", "br.w", "braf.w", 0x18, I32, simm7, zero>;
 let cx = 0, cx2 = 1 in
-defm BRCFD : BCRm<"br${cf}.d", "br.d", "braf.d", 0x18, I64, simm7fp>;
+defm BRCFD : BCRm<"br${cf}.d", "br.d", "braf.d", 0x18, I64, simm7fp, zerofp>;
 let cx = 1, cx2 = 1 in
-defm BRCFS : BCRm<"br${cf}.s", "br.s", "braf.s", 0x18, F32, simm7fp>;
+defm BRCFS : BCRm<"br${cf}.s", "br.s", "braf.s", 0x18, F32, simm7fp, zerofp>;
 
 // Section 8.8.5 - BSIC (Branch and Save IC)
 let isCall = 1, hasSideEffects = 0, DecoderMethod = "DecodeCall" in

llvm/lib/Target/VE/VERegisterInfo.td

@@ -112,10 +112,21 @@ foreach I = 0-63 in
                    DwarfRegNum<[I]>;
 
 // Generic integer registers - 64 bits wide
-let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in
-foreach I = 0-63 in
-  def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)],
-                   ["s"#I]>, DwarfRegNum<[I]>;
+let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in {
+  // Several registers have specific names, so add them to one of aliases.
+  def SX8 : VEReg<8, "s8", [SW8, SF8], ["s8", "sl"]>, DwarfRegNum<[8]>;
+  def SX9 : VEReg<9, "s9", [SW9, SF9], ["s9", "fp"]>, DwarfRegNum<[9]>;
+  def SX10 : VEReg<10, "s10", [SW10, SF10], ["s10", "lr"]>, DwarfRegNum<[10]>;
+  def SX11 : VEReg<11, "s11", [SW11, SF11], ["s11", "sp"]>, DwarfRegNum<[11]>;
+  def SX14 : VEReg<14, "s14", [SW14, SF14], ["s14", "tp"]>, DwarfRegNum<[14]>;
+  def SX15 : VEReg<15, "s15", [SW15, SF15], ["s15", "got"]>, DwarfRegNum<[15]>;
+  def SX16 : VEReg<16, "s16", [SW16, SF16], ["s16", "plt"]>, DwarfRegNum<[16]>;
+
+  // Other generic registers.
+  foreach I = { 0-7, 12-13, 17-63 } in
+    def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)],
+                     ["s"#I]>, DwarfRegNum<[I]>;
+}
 
 // Aliases of the S* registers used to hold 128-bit for values (long doubles).
 // Following foreach represents something like:

llvm/test/MC/VE/BCR.s

@@ -19,6 +19,10 @@ braf.d.nt 224
 # CHECK-ENCODING: encoding: [0xe0,0x00,0x00,0x00,0x94,0x17,0xc1,0x18]
 brgt.s 23, %s20, 224
 
+# CHECK-INST: brlt.l %s18, 0, -224
+# CHECK-ENCODING: encoding: [0x20,0xff,0xff,0xff,0x00,0x92,0x02,0x18]
+brlt.l %s18, 0, -224
+
 # CHECK-INST: brlt.l.t 23, %s20, -224
 # CHECK-ENCODING: encoding: [0x20,0xff,0xff,0xff,0x94,0x17,0x32,0x18]
 brlt.l.t 23, %s20, -224
@@ -31,6 +35,10 @@ brne.w.nt 23, %s20, 8192
 # CHECK-ENCODING: encoding: [0x20,0xff,0xff,0xff,0x94,0x17,0x44,0x18]
 breq.d 23, %s20, -224
 
+# CHECK-INST: breq.d %s20, 0, -224
+# CHECK-ENCODING: encoding: [0x20,0xff,0xff,0xff,0x00,0x94,0x44,0x18]
+breq.d %s20, 0, -224
+
 # CHECK-INST: brge.s.t 23, %s20, 8192
 # CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x94,0x17,0xf5,0x18]
 brge.s.t 23, %s20, 8192

llvm/test/MC/VE/register.s

@@ -0,0 +1,26 @@
+# RUN: llvm-mc -triple=ve %s -o - | FileCheck %s
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+### Test registers with specific names like "%sp"
+
+        subu.l %fp, %sp, %s0
+        brge.l.t %sp, %sl, 1f
+        ld %s63, 0x18(,%tp)
+1:
+        or %got, 0, %plt
+        b.l (,%lr)
+
+
+# CHECK:        subu.l %s9, %s11, %s0
+# CHECK-NEXT:   brge.l.t %s11, %s8, .Ltmp0
+# CHECK-NEXT:   ld %s63, 24(, %s14)
+# CHECK-NEXT: .Ltmp0:
+# CHECK-NEXT:   or %s15, 0, %s16
+# CHECK-NEXT:   b.l (, %s10)
+
+# CHECK-INST:        subu.l %s9, %s11, %s0
+# CHECK-INST-NEXT:   brge.l.t %s11, %s8, 16
+# CHECK-INST-NEXT:   ld %s63, 24(, %s14)
+# CHECK-INST-NEXT:   or %s15, 0, %s16
+# CHECK-INST-NEXT:   b.l (, %s10)

llvm/test/MC/VE/sym-br.s

@@ -1,10 +1,16 @@
 # RUN: llvm-mc -triple=ve %s -o - | FileCheck %s
 # RUN: llvm-mc -triple=ve -filetype=obj %s -o - | llvm-objdump -r - | FileCheck %s --check-prefix=CHECK-OBJ
 
+        b.l.t tgt
+        br.l.t tgt2
         b.l.t tgt(, %s1)
         b.l.t tgt+24(, %s1)
-# CHECK: b.l.t tgt(, %s1)
+# CHECK: b.l.t tgt
+# CHECK-NEXT: br.l.t tgt2
+# CHECK-NEXT: b.l.t tgt(, %s1)
 # CHECK-NEXT: b.l.t tgt+24(, %s1)
 
 # CHECK-OBJ: 0 R_VE_REFLONG tgt
-# CHECK-OBJ-NEXT: 8 R_VE_REFLONG tgt+0x18
+# CHECK-OBJ: 8 R_VE_PC_LO32 tgt2
+# CHECK-OBJ: 10 R_VE_REFLONG tgt
+# CHECK-OBJ: 18 R_VE_REFLONG tgt+0x18

mlir/include/mlir/Analysis/Liveness.h

@@ -86,7 +86,7 @@ class Liveness {
 
 private:
   /// Initializes the internal mappings.
-  void build(MutableArrayRef<Region> regions);
+  void build();
 
 private:
   /// The operation this analysis was constructed from.

mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td

@@ -482,13 +482,18 @@ def OpenACC_UpdateOp : OpenACC_Op<"update", [AttrSizedOperandSegments]> {
                        Variadic<IntOrIndex>:$waitOperands,
                        UnitAttr:$async,
                        UnitAttr:$wait,
+                       Variadic<IntOrIndex>:$deviceTypeOperands,
+                       Optional<I1>:$ifCond,
                        Variadic<AnyType>:$hostOperands,
                        Variadic<AnyType>:$deviceOperands,
                        UnitAttr:$ifPresent);
 
   let assemblyFormat = [{
+    ( `if` `(` $ifCond^ `)` )?
     ( `async` `(` $asyncOperand^ `:` type($asyncOperand) `)` )?
     ( `wait_devnum` `(` $waitDevnum^ `:` type($waitDevnum) `)` )?
+    ( `device_type` `(` $deviceTypeOperands^ `:`
+        type($deviceTypeOperands) `)` )?
     ( `wait` `(` $waitOperands^ `:` type($waitOperands) `)` )?
     ( `host` `(` $hostOperands^ `:` type($hostOperands) `)` )?
     ( `device` `(` $deviceOperands^ `:` type($deviceOperands) `)` )?

mlir/include/mlir/IR/Block.h

@@ -254,7 +254,7 @@ class Block : public IRObjectWithUseList<BlockOperand>,
   typename std::enable_if<std::is_same<RetT, void>::value, RetT>::type
   walk(Block::iterator begin, Block::iterator end, FnT &&callback) {
     for (auto &op : llvm::make_early_inc_range(llvm::make_range(begin, end)))
-      detail::walkOperations(&op, callback);
+      detail::walk(&op, callback);
   }
 
   /// Walk the operations in the specified [begin, end) range of this block in
@@ -265,7 +265,7 @@ class Block : public IRObjectWithUseList<BlockOperand>,
   typename std::enable_if<std::is_same<RetT, WalkResult>::value, RetT>::type
   walk(Block::iterator begin, Block::iterator end, FnT &&callback) {
     for (auto &op : llvm::make_early_inc_range(llvm::make_range(begin, end)))
-      if (detail::walkOperations(&op, callback).wasInterrupted())
+      if (detail::walk(&op, callback).wasInterrupted())
         return WalkResult::interrupt();
     return WalkResult::advance();
   }

mlir/include/mlir/IR/Operation.h

@@ -520,7 +520,7 @@ class Operation final
   ///       });
   template <typename FnT, typename RetT = detail::walkResultType<FnT>>
   RetT walk(FnT &&callback) {
-    return detail::walkOperations(this, std::forward<FnT>(callback));
+    return detail::walk(this, std::forward<FnT>(callback));
   }
 
   //===--------------------------------------------------------------------===//