Merged master:53e92b4c0efc into amd-gfx:20722fb27f2e

Local branch amd-gfx 20722fb Merged master:50cc9a0e6124 into amd-gfx:0438057f7745
Remote branch master 53e92b4 [InstCombine] (~A & B) ^ A -> A | B

compiler-rt/test/asan/TestCases/Linux/odr-violation.cpp

@@ -1,7 +1,7 @@
 // FIXME: https://code.google.com/p/address-sanitizer/issues/detail?id=316
 // XFAIL: android
 // Fails with debug checks: https://bugs.llvm.org/show_bug.cgi?id=46862
-// XFAIL: !compiler-rt-optimized
+// XFAIL: !compiler-rt-optimized && !riscv64
 //
 // We use fast_unwind_on_malloc=0 to have full unwinding even w/o frame
 // pointers. This setting is not on by default because it's too expensive.

compiler-rt/test/asan/TestCases/Linux/odr-vtable.cpp

@@ -1,5 +1,5 @@
 // Fails with debug checks: https://bugs.llvm.org/show_bug.cgi?id=46862
-// XFAIL: !compiler-rt-optimized
+// XFAIL: !compiler-rt-optimized && !riscv64
 
 // RUN: %clangxx_asan -fno-rtti -DBUILD_SO1 -fPIC -shared %s -o %dynamiclib1
 // RUN: %clangxx_asan -fno-rtti -DBUILD_SO2 -fPIC -shared %s -o %dynamiclib2

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

@@ -3335,6 +3335,10 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) {
       match(Op1, m_Not(m_Specific(A))))
     return BinaryOperator::CreateNot(Builder.CreateAnd(A, B));
 
+  // (~A & B) ^ A --> A | B -- There are 4 commuted variants.
+  if (match(&I, m_c_Xor(m_c_And(m_Not(m_Value(A)), m_Value(B)), m_Deferred(A))))
+    return BinaryOperator::CreateOr(A, B);
+
   // (A | B) ^ (A | C) --> (B ^ C) & ~A -- There are 4 commuted variants.
   // TODO: Loosen one-use restriction if common operand is a constant.
   Value *D;

llvm/test/Transforms/InstCombine/xor.ll

@@ -1176,9 +1176,7 @@ define i8 @not_ashr_wrong_const(i8 %x) {
 
 define <2 x i32> @xor_andn_commute1(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: @xor_andn_commute1(
-; CHECK-NEXT:    [[NOTA:%.*]] = xor <2 x i32> [[A:%.*]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[R:%.*]] = and <2 x i32> [[NOTA]], [[B:%.*]]
-; CHECK-NEXT:    [[Z:%.*]] = xor <2 x i32> [[R]], [[A]]
+; CHECK-NEXT:    [[Z:%.*]] = or <2 x i32> [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    ret <2 x i32> [[Z]]
 ;
   %nota = xor <2 x i32> %a, <i32 -1, i32 -1>
@@ -1192,9 +1190,7 @@ define <2 x i32> @xor_andn_commute1(<2 x i32> %a, <2 x i32> %b) {
 define i33 @xor_andn_commute2(i33 %a, i33 %pb) {
 ; CHECK-LABEL: @xor_andn_commute2(
 ; CHECK-NEXT:    [[B:%.*]] = udiv i33 42, [[PB:%.*]]
-; CHECK-NEXT:    [[NOTA:%.*]] = xor i33 [[A:%.*]], -1
-; CHECK-NEXT:    [[R:%.*]] = and i33 [[B]], [[NOTA]]
-; CHECK-NEXT:    [[Z:%.*]] = xor i33 [[R]], [[A]]
+; CHECK-NEXT:    [[Z:%.*]] = or i33 [[B]], [[A:%.*]]
 ; CHECK-NEXT:    ret i33 [[Z]]
 ;
   %b = udiv i33 42, %pb ; thwart complexity-based canonicalization
@@ -1209,9 +1205,7 @@ define i33 @xor_andn_commute2(i33 %a, i33 %pb) {
 define i32 @xor_andn_commute3(i32 %pa, i32 %b) {
 ; CHECK-LABEL: @xor_andn_commute3(
 ; CHECK-NEXT:    [[A:%.*]] = udiv i32 42, [[PA:%.*]]
-; CHECK-NEXT:    [[NOTA:%.*]] = xor i32 [[A]], -1
-; CHECK-NEXT:    [[R:%.*]] = and i32 [[NOTA]], [[B:%.*]]
-; CHECK-NEXT:    [[Z:%.*]] = xor i32 [[A]], [[R]]
+; CHECK-NEXT:    [[Z:%.*]] = or i32 [[A]], [[B:%.*]]
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
   %a = udiv i32 42, %pa ; thwart complexity-based canonicalization
@@ -1227,9 +1221,7 @@ define i32 @xor_andn_commute4(i32 %pa, i32 %pb) {
 ; CHECK-LABEL: @xor_andn_commute4(
 ; CHECK-NEXT:    [[A:%.*]] = udiv i32 42, [[PA:%.*]]
 ; CHECK-NEXT:    [[B:%.*]] = udiv i32 42, [[PB:%.*]]
-; CHECK-NEXT:    [[NOTA:%.*]] = xor i32 [[A]], -1
-; CHECK-NEXT:    [[R:%.*]] = and i32 [[B]], [[NOTA]]
-; CHECK-NEXT:    [[Z:%.*]] = xor i32 [[A]], [[R]]
+; CHECK-NEXT:    [[Z:%.*]] = or i32 [[A]], [[B]]
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
   %a = udiv i32 42, %pa ; thwart complexity-based canonicalization

llvm/unittests/Analysis/TFUtilsTest.cpp

@@ -57,7 +57,7 @@ TEST(TFUtilsTest, LoadAndExecuteTest) {
     auto ER = Evaluator.evaluate();
     EXPECT_TRUE(ER.hasValue());
     float Ret = *ER->getTensorValue<float>(0);
-    EXPECT_EQ(static_cast<size_t>(Ret), 80);
+    EXPECT_EQ(static_cast<int64_t>(Ret), 80);
     EXPECT_EQ(ER->getUntypedTensorValue(0),
               reinterpret_cast<const void *>(ER->getTensorValue<float>(0)));
   }
@@ -72,7 +72,7 @@ TEST(TFUtilsTest, LoadAndExecuteTest) {
     auto ER = Evaluator.evaluate();
     EXPECT_TRUE(ER.hasValue());
     float Ret = *ER->getTensorValue<float>(0);
-    EXPECT_EQ(static_cast<size_t>(Ret), 80);
+    EXPECT_EQ(static_cast<int64_t>(Ret), 80);
   }
 }
 
@@ -135,10 +135,10 @@ TEST(TFUtilsTest, TensorSpecSizesAndTypes) {
   auto Spec3DLarge = TensorSpec::createSpec<float>("Hi3", {2, 4, 10});
   EXPECT_TRUE(Spec1D.isElementType<int16_t>());
   EXPECT_FALSE(Spec3DLarge.isElementType<double>());
-  EXPECT_EQ(Spec1D.getElementCount(), 1);
-  EXPECT_EQ(Spec2D.getElementCount(), 1);
-  EXPECT_EQ(Spec1DLarge.getElementCount(), 10);
-  EXPECT_EQ(Spec3DLarge.getElementCount(), 80);
+  EXPECT_EQ(Spec1D.getElementCount(), 1U);
+  EXPECT_EQ(Spec2D.getElementCount(), 1U);
+  EXPECT_EQ(Spec1DLarge.getElementCount(), 10U);
+  EXPECT_EQ(Spec3DLarge.getElementCount(), 80U);
   EXPECT_EQ(Spec3DLarge.getElementByteSize(), sizeof(float));
   EXPECT_EQ(Spec1D.getElementByteSize(), sizeof(int16_t));
 }