Merged main:fce9dd6b2521 into amd-gfx:d697cf024dfc

Local branch amd-gfx d697cf0 Merged main:f333736757e9 into amd-gfx:f590b57df705
Remote branch main fce9dd6 [mlir][NFC] Remove StandardTypes.h now that all usages point to BuiltinTypes.h

llvm/docs/HowToUpdateDebugInfo.rst

@@ -342,8 +342,8 @@ A variant of the ``debugify`` utility described in
 :ref:`Mutation testing for IR-level transformations<IRDebugify>` can be used
 for MIR-level transformations as well: much like the IR-level pass,
 ``mir-debugify`` inserts sequentially increasing line locations to each
-``MachineInstr`` in a ``Module``. And the MIR-level ``mir-check-debugify`` is
-similar to IR-level ``check-debugify`` pass.
+``MachineInstr`` in a ``Module`` (although there is no equivalent MIR-level
+``check-debugify`` pass).
 
 For example, here is a snippet before:
 
@@ -403,32 +403,16 @@ and ``-start-after``. For example:
   $ llc -debugify-and-strip-all-safe -run-pass=... <other llc args>
   $ llc -debugify-and-strip-all-safe -O1 <other llc args>
 
-If you want to check it after each pass in a pipeline, use
-``-debugify-check-and-strip-all-safe``. This can also be combined with
-``-start-before`` and ``-start-after``. For example:
-
-.. code-block:: bash
-
-  $ llc -debugify-check-and-strip-all-safe -run-pass=... <other llc args>
-  $ llc -debugify-check-and-strip-all-safe -O1 <other llc args>
-
-To check all debug info from a test, use ``mir-check-debugify``, like:
-
-.. code-block:: bash
-
-  $ llc -run-pass=mir-debugify,other-pass,mir-check-debugify
-
 To strip out all debug info from a test, use ``mir-strip-debug``, like:
 
 .. code-block:: bash
 
   $ llc -run-pass=mir-debugify,other-pass,mir-strip-debug
 
-It can be useful to combine ``mir-debugify``, ``mir-check-debugify`` and/or
-``mir-strip-debug`` to identify backend transformations which break in
-the presence of debug info. For example, to run the AArch64 backend tests
-with all normal passes "sandwiched" in between MIRDebugify and
-MIRStripDebugify mutation passes, run:
+It can be useful to combine ``mir-debugify`` and ``mir-strip-debug`` to
+identify backend transformations which break in the presence of debug info.
+For example, to run the AArch64 backend tests with all normal passes
+"sandwiched" in between MIRDebugify and MIRStripDebugify mutation passes, run:
 
 .. code-block:: bash
 

llvm/include/llvm/CodeGen/Passes.h

@@ -482,9 +482,6 @@ namespace llvm {
   /// info was generated by another source such as clang.
   ModulePass *createStripDebugMachineModulePass(bool OnlyDebugified);
 
-  /// Creates MIR Check Debug pass. \see MachineCheckDebugify.cpp
-  ModulePass *createCheckDebugMachineModulePass();
-
   /// The pass fixups statepoint machine instruction to replace usage of
   /// caller saved registers with stack slots.
   extern char &FixupStatepointCallerSavedID;

llvm/include/llvm/CodeGen/TargetPassConfig.h

@@ -313,9 +313,6 @@ class TargetPassConfig : public ImmutablePass {
   /// Add a pass to remove debug info from the MIR.
   void addStripDebugPass();
 
-  /// Add a pass to check synthesized debug info for MIR.
-  void addCheckDebugPass();
-
   /// Add standard passes before a pass that's about to be added. For example,
   /// the DebugifyMachineModulePass if it is enabled.
   void addMachinePrePasses(bool AllowDebugify = true);

llvm/include/llvm/IR/IntrinsicsRISCV.td

@@ -124,7 +124,7 @@ let TargetPrefix = "riscv" in {
   class RISCVBinaryAAXMask
        : Intrinsic<[llvm_anyvector_ty],
                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
-                    llvm_anyvector_ty, llvm_anyint_ty],
+                    LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
                    [IntrNoMem]>, RISCVVIntrinsic {
     let ExtendOperand = 3;
   }
@@ -141,15 +141,16 @@ let TargetPrefix = "riscv" in {
   class RISCVBinaryABXMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
-                     llvm_anyvector_ty, llvm_anyint_ty],
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic {
     let ExtendOperand = 3;
   }
   // For binary operations with V0 as input.
   // Input: (vector_in, vector_in/scalar_in, V0, vl)
   class RISCVBinaryWithV0
         : Intrinsic<[llvm_anyvector_ty],
-                    [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
+                    [LLVMMatchType<0>, llvm_any_ty,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                      llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic {
     let ExtendOperand = 2;
@@ -158,8 +159,9 @@ let TargetPrefix = "riscv" in {
   // Output: (mask type output)
   // Input: (vector_in, vector_in/scalar_in, V0, vl)
   class RISCVBinaryMOutWithV0
-        :Intrinsic<[llvm_anyvector_ty],
-                   [llvm_anyvector_ty, llvm_any_ty, LLVMMatchType<0>,
+        :Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
+                   [llvm_anyvector_ty, llvm_any_ty,
+                    LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                     llvm_anyint_ty],
                    [IntrNoMem]>, RISCVVIntrinsic {
     let ExtendOperand = 2;
@@ -168,7 +170,7 @@ let TargetPrefix = "riscv" in {
   // Output: (mask type output)
   // Input: (vector_in, vector_in/scalar_in, vl)
   class RISCVBinaryMOut
-        : Intrinsic<[llvm_anyvector_ty],
+        : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
                     [llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic {
     let ExtendOperand = 2;
@@ -237,6 +239,20 @@ let TargetPrefix = "riscv" in {
   defm vmaxu : RISCVBinaryAAX;
   defm vmax : RISCVBinaryAAX;
 
+  defm vmul : RISCVBinaryAAX;
+  defm vmulh : RISCVBinaryAAX;
+  defm vmulhu : RISCVBinaryAAX;
+  defm vmulhsu : RISCVBinaryAAX;
+
+  defm vdivu : RISCVBinaryAAX;
+  defm vdiv : RISCVBinaryAAX;
+  defm vremu : RISCVBinaryAAX;
+  defm vrem : RISCVBinaryAAX;
+
+  defm vwmul : RISCVBinaryABX;
+  defm vwmulu : RISCVBinaryABX;
+  defm vwmulsu : RISCVBinaryABX;
+
   defm vfadd : RISCVBinaryAAX;
   defm vfsub : RISCVBinaryAAX;
   defm vfrsub : RISCVBinaryAAX;

llvm/include/llvm/InitializePasses.h

@@ -112,7 +112,6 @@ void initializeCallGraphViewerPass(PassRegistry&);
 void initializeCallGraphWrapperPassPass(PassRegistry&);
 void initializeCallSiteSplittingLegacyPassPass(PassRegistry&);
 void initializeCalledValuePropagationLegacyPassPass(PassRegistry &);
-void initializeCheckDebugMachineModulePass(PassRegistry &);
 void initializeCodeGenPreparePass(PassRegistry&);
 void initializeConstantHoistingLegacyPassPass(PassRegistry&);
 void initializeConstantMergeLegacyPassPass(PassRegistry&);

llvm/lib/CodeGen/CMakeLists.txt

@@ -74,7 +74,6 @@ add_llvm_component_library(LLVMCodeGen
   MachineCombiner.cpp
   MachineCopyPropagation.cpp
   MachineCSE.cpp
-  MachineCheckDebugify.cpp
   MachineDebugify.cpp
   MachineDominanceFrontier.cpp
   MachineDominators.cpp

llvm/lib/CodeGen/CodeGen.cpp

@@ -25,7 +25,6 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeBranchRelaxationPass(Registry);
   initializeCFGuardLongjmpPass(Registry);
   initializeCFIInstrInserterPass(Registry);
-  initializeCheckDebugMachineModulePass(Registry);
   initializeCodeGenPreparePass(Registry);
   initializeDeadMachineInstructionElimPass(Registry);
   initializeDebugifyMachineModulePass(Registry);

llvm/lib/CodeGen/MachineDebugify.cpp

@@ -14,7 +14,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -90,11 +89,10 @@ bool applyDebugifyMetadataToMachineFunction(MachineModuleInfo &MMI,
   // Do this by introducing debug uses of each register definition. If that is
   // not possible (e.g. we have a phi or a meta instruction), emit a constant.
   uint64_t NextImm = 0;
-  SmallSet<DILocalVariable *, 16> VarSet;
   const MCInstrDesc &DbgValDesc = TII.get(TargetOpcode::DBG_VALUE);
   for (MachineBasicBlock &MBB : MF) {
     MachineBasicBlock::iterator FirstNonPHIIt = MBB.getFirstNonPHI();
-    for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
+    for (auto I = MBB.begin(), E = MBB.end(); I != E; ) {
       MachineInstr &MI = *I;
       ++I;
 
@@ -115,7 +113,6 @@ bool applyDebugifyMetadataToMachineFunction(MachineModuleInfo &MMI,
         Line = EarliestDVI->getDebugLoc().getLine();
       DILocalVariable *LocalVar = Line2Var[Line];
       assert(LocalVar && "No variable for current line?");
-      VarSet.insert(LocalVar);
 
       // Emit DBG_VALUEs for register definitions.
       SmallVector<MachineOperand *, 4> RegDefs;
@@ -135,33 +132,6 @@ bool applyDebugifyMetadataToMachineFunction(MachineModuleInfo &MMI,
     }
   }
 
-  // Here we save the number of lines and variables into "llvm.mir.debugify".
-  // It is useful for mir-check-debugify.
-  NamedMDNode *NMD = M.getNamedMetadata("llvm.mir.debugify");
-  IntegerType *Int32Ty = Type::getInt32Ty(Ctx);
-  if (!NMD) {
-    NMD = M.getOrInsertNamedMetadata("llvm.mir.debugify");
-    auto addDebugifyOperand = [&](unsigned N) {
-      NMD->addOperand(MDNode::get(
-          Ctx, ValueAsMetadata::getConstant(ConstantInt::get(Int32Ty, N))));
-    };
-    // Add number of lines.
-    addDebugifyOperand(NextLine - 1);
-    // Add number of variables.
-    addDebugifyOperand(VarSet.size());
-  } else {
-    assert(NMD->getNumOperands() == 2 &&
-           "llvm.mir.debugify should have exactly 2 operands!");
-    auto setDebugifyOperand = [&](unsigned Idx, unsigned N) {
-      NMD->setOperand(Idx, MDNode::get(Ctx, ValueAsMetadata::getConstant(
-                                                ConstantInt::get(Int32Ty, N))));
-    };
-    // Set number of lines.
-    setDebugifyOperand(0, NextLine - 1);
-    // Set number of variables.
-    setDebugifyOperand(1, VarSet.size());
-  }
-
   return true;
 }
 

llvm/lib/CodeGen/TargetPassConfig.cpp

@@ -120,12 +120,6 @@ static cl::opt<cl::boolOrDefault> DebugifyAndStripAll(
         "Debugify MIR before and Strip debug after "
         "each pass except those known to be unsafe when debug info is present"),
     cl::ZeroOrMore);
-static cl::opt<cl::boolOrDefault> DebugifyCheckAndStripAll(
-    "debugify-check-and-strip-all-safe", cl::Hidden,
-    cl::desc(
-        "Debugify MIR before, by checking and stripping the debug info after, "
-        "each pass except those known to be unsafe when debug info is present"),
-    cl::ZeroOrMore);
 enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
 // Enable or disable the MachineOutliner.
 static cl::opt<RunOutliner> EnableMachineOutliner(
@@ -631,26 +625,15 @@ void TargetPassConfig::addStripDebugPass() {
   PM->add(createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
 }
 
-void TargetPassConfig::addCheckDebugPass() {
-  PM->add(createCheckDebugMachineModulePass());
-}
-
 void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
-  if (AllowDebugify && DebugifyIsSafe &&
-      (DebugifyAndStripAll == cl::BOU_TRUE ||
-       DebugifyCheckAndStripAll == cl::BOU_TRUE))
+  if (AllowDebugify && DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
     addDebugifyPass();
 }
 
 void TargetPassConfig::addMachinePostPasses(const std::string &Banner,
                                             bool AllowVerify, bool AllowStrip) {
-  if (DebugifyIsSafe) {
-    if (DebugifyCheckAndStripAll == cl::BOU_TRUE) {
-      addCheckDebugPass();
-      addStripDebugPass();
-    } else if (DebugifyAndStripAll == cl::BOU_TRUE)
-      addStripDebugPass();
-  }
+  if (DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
+    addStripDebugPass();
   if (AllowVerify)
     addVerifyPass(Banner);
 }