forked from GPUOpen-Drivers/llvm-project
-
Notifications
You must be signed in to change notification settings - Fork 0
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merged master:a8ca0ec2670 into amd-gfx:28c0fb04db7
Local branch amd-gfx 28c0fb0 Merged master:77e1181df44 into amd-gfx:216ed1d226d Remote branch master a8ca0ec AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
- Loading branch information
Showing
5 changed files
with
164 additions
and
5 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,153 @@ | ||
//=== lib/CodeGen/GlobalISel/AMDGPURegBankCombiner.cpp ---------------===// | ||
// | ||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
//===----------------------------------------------------------------------===// | ||
// | ||
// This pass does combining of machine instructions at the generic MI level, | ||
// after register banks are known. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
|
||
#include "AMDGPUTargetMachine.h" | ||
#include "AMDGPULegalizerInfo.h" | ||
#include "llvm/CodeGen/GlobalISel/Combiner.h" | ||
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h" | ||
#include "llvm/CodeGen/GlobalISel/CombinerInfo.h" | ||
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h" | ||
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" | ||
#include "llvm/CodeGen/MachineDominators.h" | ||
#include "llvm/CodeGen/MachineFunctionPass.h" | ||
#include "llvm/CodeGen/TargetPassConfig.h" | ||
#include "llvm/Support/Debug.h" | ||
#include "MCTargetDesc/AMDGPUMCTargetDesc.h" | ||
|
||
#define DEBUG_TYPE "amdgpu-regbank-combiner" | ||
|
||
using namespace llvm; | ||
using namespace MIPatternMatch; | ||
|
||
|
||
#define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_DEPS | ||
#include "AMDGPUGenRegBankGICombiner.inc" | ||
#undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_DEPS | ||
|
||
namespace { | ||
#define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_H | ||
#include "AMDGPUGenRegBankGICombiner.inc" | ||
#undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_H | ||
|
||
class AMDGPURegBankCombinerInfo : public CombinerInfo { | ||
GISelKnownBits *KB; | ||
MachineDominatorTree *MDT; | ||
|
||
public: | ||
AMDGPUGenRegBankCombinerHelper Generated; | ||
|
||
AMDGPURegBankCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize, | ||
const AMDGPULegalizerInfo *LI, | ||
GISelKnownBits *KB, MachineDominatorTree *MDT) | ||
: CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true, | ||
/*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize), | ||
KB(KB), MDT(MDT) { | ||
if (!Generated.parseCommandLineOption()) | ||
report_fatal_error("Invalid rule identifier"); | ||
} | ||
|
||
bool combine(GISelChangeObserver &Observer, MachineInstr &MI, | ||
MachineIRBuilder &B) const override; | ||
}; | ||
|
||
bool AMDGPURegBankCombinerInfo::combine(GISelChangeObserver &Observer, | ||
MachineInstr &MI, | ||
MachineIRBuilder &B) const { | ||
CombinerHelper Helper(Observer, B, KB, MDT); | ||
|
||
if (Generated.tryCombineAll(Observer, MI, B, Helper)) | ||
return true; | ||
|
||
return false; | ||
} | ||
|
||
#define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_CPP | ||
#include "AMDGPUGenRegBankGICombiner.inc" | ||
#undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_CPP | ||
|
||
// Pass boilerplate | ||
// ================ | ||
|
||
class AMDGPURegBankCombiner : public MachineFunctionPass { | ||
public: | ||
static char ID; | ||
|
||
AMDGPURegBankCombiner(bool IsOptNone = false); | ||
|
||
StringRef getPassName() const override { | ||
return "AMDGPURegBankCombiner"; | ||
} | ||
|
||
bool runOnMachineFunction(MachineFunction &MF) override; | ||
|
||
void getAnalysisUsage(AnalysisUsage &AU) const override; | ||
private: | ||
bool IsOptNone; | ||
}; | ||
} // end anonymous namespace | ||
|
||
void AMDGPURegBankCombiner::getAnalysisUsage(AnalysisUsage &AU) const { | ||
AU.addRequired<TargetPassConfig>(); | ||
AU.setPreservesCFG(); | ||
getSelectionDAGFallbackAnalysisUsage(AU); | ||
AU.addRequired<GISelKnownBitsAnalysis>(); | ||
AU.addPreserved<GISelKnownBitsAnalysis>(); | ||
if (!IsOptNone) { | ||
AU.addRequired<MachineDominatorTree>(); | ||
AU.addPreserved<MachineDominatorTree>(); | ||
} | ||
MachineFunctionPass::getAnalysisUsage(AU); | ||
} | ||
|
||
AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone) | ||
: MachineFunctionPass(ID), IsOptNone(IsOptNone) { | ||
initializeAMDGPURegBankCombinerPass(*PassRegistry::getPassRegistry()); | ||
} | ||
|
||
bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) { | ||
if (MF.getProperties().hasProperty( | ||
MachineFunctionProperties::Property::FailedISel)) | ||
return false; | ||
auto *TPC = &getAnalysis<TargetPassConfig>(); | ||
const Function &F = MF.getFunction(); | ||
bool EnableOpt = | ||
MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F); | ||
|
||
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); | ||
const AMDGPULegalizerInfo *LI | ||
= static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo()); | ||
|
||
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF); | ||
MachineDominatorTree *MDT = | ||
IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>(); | ||
AMDGPURegBankCombinerInfo PCInfo(EnableOpt, F.hasOptSize(), | ||
F.hasMinSize(), LI, KB, MDT); | ||
Combiner C(PCInfo, TPC); | ||
return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr); | ||
} | ||
|
||
char AMDGPURegBankCombiner::ID = 0; | ||
INITIALIZE_PASS_BEGIN(AMDGPURegBankCombiner, DEBUG_TYPE, | ||
"Combine AMDGPU machine instrs after regbankselect", | ||
false, false) | ||
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) | ||
INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis) | ||
INITIALIZE_PASS_END(AMDGPURegBankCombiner, DEBUG_TYPE, | ||
"Combine AMDGPU machine instrs after regbankselect", false, | ||
false) | ||
|
||
namespace llvm { | ||
FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone) { | ||
return new AMDGPURegBankCombiner(IsOptNone); | ||
} | ||
} // end namespace llvm |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters