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[AMDGPU] Disable endcf collapse again
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This was reenabled and supposedly fixed by D76154 but it is still
causing problems.

Change-Id: Iefe2abd2da7db126915743eec435053c0d076266
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jayfoad authored and trenouf committed Apr 9, 2020
1 parent c263608 commit c7c3927
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Showing 2 changed files with 5 additions and 3 deletions.
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,7 @@ using namespace llvm;

static cl::opt<bool>
RemoveRedundantEndcf("amdgpu-remove-redundant-endcf",
cl::init(true), cl::ReallyHidden);
cl::init(false), cl::ReallyHidden);

namespace {

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6 changes: 4 additions & 2 deletions llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1
; GFX9-NEXT: s_and_saveexec_b64 s[10:11], s[4:5]
; GFX9-NEXT: s_cbranch_execz BB1_3
; GFX9-NEXT: s_cbranch_execz BB1_4
; GFX9-NEXT: ; %bb.1: ; %bb19
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v6
; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v6
Expand Down Expand Up @@ -100,7 +100,9 @@ define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3
; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
; GFX9-NEXT: s_andn2_b64 exec, exec, s[12:13]
; GFX9-NEXT: s_cbranch_execnz BB1_2
; GFX9-NEXT: BB1_3: ; %Flow3
; GFX9-NEXT: ; %bb.3: ; %Flow
; GFX9-NEXT: s_or_b64 exec, exec, s[12:13]
; GFX9-NEXT: BB1_4: ; %Flow3
; GFX9-NEXT: s_or_b64 exec, exec, s[10:11]
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
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