Merged master:7af12015ad44 into amd-gfx:93bf630eaf4b

Local branch amd-gfx 93bf630 Merged master:a399d1880bc6 into amd-gfx:3c5f340b9e99 Remote branch master 7af1201 [msan] Remove redundant test
jaebaek · Sep 25, 2020 · e6f7d95 · e6f7d95
2 parents 93bf630 + 7af1201
commit e6f7d95
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Showing 10 changed files with 260 additions and 83 deletions.
diff --git a/compiler-rt/lib/msan/tests/msan_test.cpp b/compiler-rt/lib/msan/tests/msan_test.cpp
@@ -587,20 +587,6 @@ LargeStruct LargeRetTest() {
   return res;
 }
 
-TEST(MemorySanitizer, strcmp) {
-  char s1[10];
-  char s2[10];
-  strncpy(s1, "foo", 10);
-  s2[0] = 'f';
-  s2[1] = 'n';
-  EXPECT_GT(strcmp(s1, s2), 0);
-  s2[1] = 'o';
-  int res;
-  EXPECT_UMR(res = strcmp(s1, s2));
-  EXPECT_NOT_POISONED(res);
-  EXPECT_EQ(strncmp(s1, s2, 1), 0);
-}
-
 TEST(MemorySanitizer, LargeRet) {
   LargeStruct a = LargeRetTest();
   EXPECT_POISONED(a.x[0]);
@@ -1114,6 +1100,7 @@ TEST_P(MemorySanitizerIpTest, recvmsg) {
   } while (0)
 
 TEST(MemorySanitizer, gethostent) {
+  sethostent(0);
   struct hostent *he = gethostent();
   ASSERT_NE((void *)NULL, he);
   EXPECT_HOSTENT_NOT_POISONED(he);
@@ -1177,6 +1164,7 @@ TEST(MemorySanitizer, gethostbyaddr) {
 
 #if !defined(__NetBSD__)
 TEST(MemorySanitizer, gethostent_r) {
+  sethostent(0);
   char buf[2000];
   struct hostent he;
   struct hostent *result;

diff --git a/flang/unittests/Frontend/CMakeLists.txt b/flang/unittests/Frontend/CMakeLists.txt
@@ -6,5 +6,6 @@ target_link_libraries(FlangFrontendTests
   PRIVATE
   LLVMSupport
   clangBasic
+  clangFrontend
   flangFrontend
   flangFrontendTool)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2971,6 +2971,24 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
       return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
     }
   }
+  case AArch64::G_DUP: {
+    // When the scalar of G_DUP is an s8/s16 gpr, they can't be selected by
+    // imported patterns. Do it manually here. Avoiding generating s16 gpr is
+    // difficult because at RBS we may end up pessimizing the fpr case if we
+    // decided to add an anyextend to fix this. Manual selection is the most
+    // robust solution for now.
+    Register SrcReg = I.getOperand(1).getReg();
+    if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() != AArch64::GPRRegBankID)
+      return false; // We expect the fpr regbank case to be imported.
+    LLT SrcTy = MRI.getType(SrcReg);
+    if (SrcTy.getSizeInBits() == 16)
+      I.setDesc(TII.get(AArch64::DUPv8i16gpr));
+    else if (SrcTy.getSizeInBits() == 8)
+      I.setDesc(TII.get(AArch64::DUPv16i8gpr));
+    else
+      return false;
+    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+  }
   case TargetOpcode::G_INTRINSIC_TRUNC:
     return selectIntrinsicTrunc(I, MRI);
   case TargetOpcode::G_INTRINSIC_ROUND:

diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -597,11 +597,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .minScalarOrElt(0, s8); // Worst case, we need at least s8.
 
   getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
-      .legalIf([=](const LegalityQuery &Query) {
-        const LLT &VecTy = Query.Types[0];
-        // TODO: Support s8 and s16
-        return VecTy == v2s32 || VecTy == v4s32 || VecTy == v2s64;
-      });
+      .legalIf(typeInSet(0, {v8s16, v2s32, v4s32, v2s64}));
 
   getActionDefinitionsBuilder(G_BUILD_VECTOR)
       .legalFor({{v8s8, s8},

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
@@ -0,0 +1,79 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s
+
+---
+name:            v8s16
+body: |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: v8s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: %val:_(s16) = G_CONSTANT i16 42
+    ; CHECK: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
+    ; CHECK: $q0 = COPY [[IVEC]](<8 x s16>)
+    ; CHECK: RET_ReallyLR
+    %0:_(<8 x s16>) = COPY $q0
+    %1:_(s32) = G_CONSTANT i32 1
+    %val:_(s16) = G_CONSTANT i16 42
+    %2:_(<8 x s16>) = G_INSERT_VECTOR_ELT %0(<8 x s16>), %val(s16), %1(s32)
+    $q0 = COPY %2(<8 x s16>)
+    RET_ReallyLR
+...
+---
+name:            v2s32
+body: |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: %val:_(s32) = G_CONSTANT i32 42
+    ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
+    ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
+    ; CHECK: RET_ReallyLR
+    %0:_(<2 x s32>) = COPY $d0
+    %1:_(s32) = G_CONSTANT i32 1
+    %val:_(s32) = G_CONSTANT i32 42
+    %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %val(s32), %1(s32)
+    $d0 = COPY %2(<2 x s32>)
+    RET_ReallyLR
+...
+---
+name:            v4s32
+body: |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: v4s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: %val:_(s32) = G_CONSTANT i32 42
+    ; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
+    ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
+    ; CHECK: RET_ReallyLR
+    %0:_(<4 x s32>) = COPY $q0
+    %1:_(s32) = G_CONSTANT i32 1
+    %val:_(s32) = G_CONSTANT i32 42
+    %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0(<4 x s32>), %val(s32), %1(s32)
+    $q0 = COPY %2(<4 x s32>)
+    RET_ReallyLR
+...
+---
+name:            v2s64
+body: |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: v2s64
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: %val:_(s64) = G_CONSTANT i64 42
+    ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s32)
+    ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
+    ; CHECK: RET_ReallyLR
+    %0:_(<2 x s64>) = COPY $q0
+    %1:_(s32) = G_CONSTANT i32 1
+    %val:_(s64) = G_CONSTANT i64 42
+    %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %0(<2 x s64>), %val(s64), %1(s32)
+    $q0 = COPY %2(<2 x s64>)
+    RET_ReallyLR
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
@@ -223,6 +223,29 @@ body:             |
     $q0 = COPY %dup(<8 x s16>)
     RET_ReallyLR implicit $q0
 
+...
+---
+name:            DUPv8i16gpr_s16_src
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $w0
+    ; Checks that we can still select the gpr variant if the scalar is an s16.
+    ; CHECK-LABEL: name: DUPv8i16gpr_s16_src
+    ; CHECK: liveins: $w0
+    ; CHECK: %copy:gpr32 = COPY $w0
+    ; CHECK: %dup:fpr128 = DUPv8i16gpr %copy
+    ; CHECK: $q0 = COPY %dup
+    ; CHECK: RET_ReallyLR implicit $q0
+    %copy:gpr(s32) = COPY $w0
+    %trunc:gpr(s16) = G_TRUNC %copy
+    %dup:fpr(<8 x s16>) = G_DUP %trunc(s16)
+    $q0 = COPY %dup(<8 x s16>)
+    RET_ReallyLR implicit $q0
+
 ...
 ---
 name:            DUPv8i8gpr
@@ -264,3 +287,26 @@ body:             |
     %dup:fpr(<16 x s8>) = G_DUP %copy(s32)
     $q0 = COPY %dup(<16 x s8>)
     RET_ReallyLR implicit $q0
+...
+---
+name:            DUPv16i8gpr_s8_src
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $w0
+    ; Check we still select the gpr variant when scalar is an s8.
+    ; CHECK-LABEL: name: DUPv16i8gpr_s8_src
+    ; CHECK: liveins: $w0
+    ; CHECK: %copy:gpr32 = COPY $w0
+    ; CHECK: %dup:fpr128 = DUPv16i8gpr %copy
+    ; CHECK: $q0 = COPY %dup
+    ; CHECK: RET_ReallyLR implicit $q0
+    %copy:gpr(s32) = COPY $w0
+    %trunc:gpr(s8) = G_TRUNC %copy
+    %dup:fpr(<16 x s8>) = G_DUP %trunc(s8)
+    $q0 = COPY %dup(<16 x s8>)
+    RET_ReallyLR implicit $q0
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
@@ -1,6 +1,33 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
+---
+name:            v8s16_fpr
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q1, $h0
 
+    ; CHECK-LABEL: name: v8s16_fpr
+    ; CHECK: liveins: $q1, $h0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub
+    ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
+    ; CHECK: $q0 = COPY [[INSvi16lane]]
+    ; CHECK: RET_ReallyLR implicit $q0
+    %0:fpr(s16) = COPY $h0
+    %1:fpr(<8 x s16>) = COPY $q1
+    %3:gpr(s32) = G_CONSTANT i32 1
+    %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s32)
+    $q0 = COPY %2(<8 x s16>)
+    RET_ReallyLR implicit $q0
+
+...
+---
 name:            v4s32_fpr
 alignment:       4
 legalized:       true

diff --git a/llvm/test/Object/Mips/abi-flags.yaml b/llvm/test/Object/Mips/abi-flags.yaml
diff --git a/llvm/test/tools/obj2yaml/ELF/mips-abi-flags.yaml b/llvm/test/tools/obj2yaml/ELF/mips-abi-flags.yaml
@@ -0,0 +1,41 @@
+## Check how obj2yaml dumps SHT_MIPS_ABIFLAGS sections.
+
+# RUN: yaml2obj %s -o %t
+# RUN: obj2yaml %t | FileCheck %s
+
+# CHECK:      Sections:
+# CHECK-NEXT:   - Name:         .MIPS.abiflags
+# CHECK-NEXT:     Type:         SHT_MIPS_ABIFLAGS
+# CHECK-NEXT:     AddressAlign: 0x0000000000000008
+# CHECK-NEXT:     EntSize:      0x0000000000000018
+# CHECK-NEXT:     ISA:          MIPS64
+# CHECK-NEXT:     ISARevision:  0x05
+# CHECK-NEXT:     ISAExtension: EXT_OCTEON3
+# CHECK-NEXT:     ASEs:         [ DSP, DSPR2, VIRT ]
+# CHECK-NEXT:     FpABI:        FP_DOUBLE
+# CHECK-NEXT:     GPRSize:      REG_64
+# CHECK-NEXT:     CPR1Size:     REG_64
+# CHECK-NEXT:     Flags1:       [ ODDSPREG ]
+# CHECK-NEXT: ...
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:    ELFDATA2MSB
+  Type:    ET_REL
+  Machine: EM_MIPS
+Sections:
+  - Name:         .MIPS.abiflags
+    Type:         SHT_MIPS_ABIFLAGS
+    AddressAlign: 8
+    Version:      0
+    ISA:          MIPS64
+    ISARevision:  5
+    ISAExtension: EXT_OCTEON3
+    ASEs:         [ DSP, DSPR2, VIRT ]
+    FpABI:        FP_DOUBLE
+    GPRSize:      REG_64
+    CPR1Size:     REG_64
+    CPR2Size:     REG_NONE
+    Flags1:       [ ODDSPREG ]
+    Flags2:       0x0