Demo for Lattice FPGA with dual core RiscV, Based on Trenz CR00103-03 Certus-NX board.
FPGA based RiscV, based on the out-of-the-box 'hello world' template from Lattice.
More info to be found on the following links :
- Trenz Cruvi Board
- Example1 - not the best example, but its a start.
- Example2 - a bit more details but based on other board.
- Propel Tools video @ Lattice - MUST SEE !
- Lattice Certus-NX
Code Content is the Propel Builder (verilog project) and the Propel SDK code (C-project)
Lattice currently is pretty lean on the base templates for propel and RiscV. This project is a try out and adds a second core and GPIO for user-button input.
C-Code is created for cpu0 and cpu1, using the created BSP packages by the Propel builder.
CPU's are communicating using the memory mapped Dualport Memory and a simple soft-metaphore: 64 bytes are send to CPU1, it re-creates the date and sends it back.
CPU0 has a USB-comport open and reports the data over serial. Holding the user botton stops CPU1.
Follow the Lattice Propel Video's to understand the work-flow for designing a RiscV on FPGA.
Key is to add the post-constrain file to constrain the IO pins of the RX/TX and User_Button pins, and add the sysmem initialisation to your C-code : load the mem-file to the two CPU's pre-initialisation.
Propel is license free, but you do need to apply for a free license via their website after registration.