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Issue#1250: Corrected alignment of multiline variable and signal declarations for align_left = no #1345

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Issue#1250: Corrected alignment of multiline variable and signal declarations for align_left = no #1345

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fd0dfa1
Issue#1250: Corrections to multiline_alignment for method _analyze_al…
JHertz5 Dec 11, 2024
09f1c42
Issue#1250: Updated tests after corrections to multiline_alignment fo…
JHertz5 Dec 11, 2024
ab75150
Merge remote-tracking branch 'origin/master' into issue-1250
JHertz5 Dec 12, 2024
29735b1
Issue#1250: Updates after merge of issue-1290.
JHertz5 Dec 12, 2024
e8192d0
Issue#1250: Updated "align_left no, align_paren no" alignment as well.
JHertz5 Dec 12, 2024
e553b8a
Issue#1250: Updated tests for signal_400.
JHertz5 Dec 12, 2024
48dd9a6
Issue#1250: Updated tests for variable_400.
JHertz5 Dec 12, 2024
4966c50
Issue#1250: Formatting.
JHertz5 Dec 12, 2024
76682e9
Merge branch 'jeremiah-c-leary:master' into issue-1250
JHertz5 Dec 12, 2024
aa299fa
Merge remote-tracking branch 'origin/master' into issue-1250
JHertz5 Dec 13, 2024
31c0202
Merge branch 'jeremiah-c-leary:master' into issue-1250
JHertz5 Dec 13, 2024
af08d03
Merge remote-tracking branch 'origin/master' into issue-1250
JHertz5 Dec 13, 2024
19b6db6
Merge branch 'jeremiah-c-leary:master' into issue-1250
JHertz5 Dec 17, 2024
daa64bf
Merge branch 'jeremiah-c-leary:master' into issue-1250
JHertz5 Dec 18, 2024
b57cf09
Merge branch 'jeremiah-c-leary:master' into issue-1250
JHertz5 Dec 19, 2024
f1b8108
Merge branch 'jeremiah-c-leary:master' into issue-1250
JHertz5 Dec 20, 2024
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Merge branch 'jeremiah-c-leary:master' into issue-1250
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46 changes: 28 additions & 18 deletions tests/signal/rule_400_test_input.fixed__align_left_no__align_paren_no.vhd
View file
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Original file line number Diff line number Diff line change
@@ -1,29 +1,39 @@
architecture rtl of fifo is

signal sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
);

signal s : MY_TYPE := (
a => '0',
ddddd => (others => '0'),
ffff => (others => '0')
a => '0',
ddddd => (others => '0'),
ffff => (others => '0')
);

signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
w_data(DataRange_c),
w_strb(ByteRange_c));

signal AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
r_user(UserRange_c), b_user(UserRange_c),
r_data(DataRange_c));

begin

end architecture rtl;
46 changes: 28 additions & 18 deletions tests/signal/rule_400_test_input.fixed__align_left_no__align_paren_yes.vhd
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,29 +1,39 @@
architecture rtl of fifo is

signal sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
);

signal s : MY_TYPE := (
a => '0',
ddddd => (others => '0'),
ffff => (others => '0')
a => '0',
ddddd => (others => '0'),
ffff => (others => '0')
);

signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
w_data(DataRange_c),
w_strb(ByteRange_c));

signal AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
r_user(UserRange_c), b_user(UserRange_c),
r_data(DataRange_c));

begin

end architecture rtl;
10 changes: 10 additions & 0 deletions tests/signal/rule_400_test_input.fixed__align_left_yes__align_paren_no.vhd
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,16 @@ architecture rtl of fifo is
ffff => (others => '0')
);

signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
w_data(DataRange_c),
w_strb(ByteRange_c));

signal AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
r_user(UserRange_c), b_user(UserRange_c),
r_data(DataRange_c));

begin

end architecture rtl;
10 changes: 10 additions & 0 deletions tests/signal/rule_400_test_input.fixed__align_left_yes__align_paren_yes.vhd
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,16 @@ architecture rtl of fifo is
ffff => (others => '0')
);

signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
w_data(DataRange_c),
w_strb(ByteRange_c));

signal AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
r_user(UserRange_c), b_user(UserRange_c),
r_data(DataRange_c));

begin

end architecture rtl;
10 changes: 10 additions & 0 deletions tests/signal/rule_400_test_input.vhd
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,16 @@ elementE(3 downto 0)(6 downto 0),
ffff => (others => '0')
);

signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
w_data(DataRange_c),
w_strb(ByteRange_c));

signal AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
r_user(UserRange_c), b_user(UserRange_c),
r_data(DataRange_c));

begin

end architecture rtl;
16 changes: 16 additions & 0 deletions tests/signal/test_rule_400.py
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,8 @@ def test_rule_400__align_left_yes__align_paren_no(self):
lExpected = []
lExpected.extend(range(5, 20))
lExpected.extend(range(22, 26))
lExpected.extend(range(28, 32))
lExpected.extend(range(34, 36))

oRule.analyze(self.oFile)
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
Expand All @@ -65,6 +67,8 @@ def test_rule_400__align_left_true__align_paren_false(self):
lExpected = []
lExpected.extend(range(5, 20))
lExpected.extend(range(22, 26))
lExpected.extend(range(28, 32))
lExpected.extend(range(34, 36))

oRule.analyze(self.oFile)
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
Expand Down Expand Up @@ -95,6 +99,8 @@ def test_rule_400__align_left_no__align_paren_no(self):
lExpected = []
lExpected.extend(range(4, 20))
lExpected.extend(range(22, 26))
lExpected.extend(range(28, 32))
lExpected.extend(range(34, 36))

oRule.analyze(self.oFile)
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
Expand All @@ -111,6 +117,8 @@ def test_rule_400__align_left_false__align_paren_false(self):
lExpected = []
lExpected.extend(range(4, 20))
lExpected.extend(range(22, 26))
lExpected.extend(range(28, 32))
lExpected.extend(range(34, 36))

oRule.analyze(self.oFile)
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
Expand Down Expand Up @@ -141,6 +149,8 @@ def test_rule_400__align_left_no__align_paren_yes(self):
lExpected = []
lExpected.extend(range(4, 20))
lExpected.extend(range(22, 26))
lExpected.extend(range(28, 32))
lExpected.extend(range(34, 36))

oRule.analyze(self.oFile)
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
Expand All @@ -157,6 +167,8 @@ def test_rule_400__align_left_false__align_paren_true(self):
lExpected = []
lExpected.extend(range(4, 20))
lExpected.extend(range(22, 26))
lExpected.extend(range(28, 32))
lExpected.extend(range(34, 36))

oRule.analyze(self.oFile)
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
Expand Down Expand Up @@ -187,6 +199,8 @@ def test_rule_400__align_left_yes__align_paren_yes(self):
lExpected = []
lExpected.extend(range(5, 20))
lExpected.extend(range(22, 26))
lExpected.extend(range(28, 32))
lExpected.extend(range(34, 36))

oRule.analyze(self.oFile)
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
Expand All @@ -203,6 +217,8 @@ def test_rule_400__align_left_true__align_paren_true(self):
lExpected = []
lExpected.extend(range(5, 20))
lExpected.extend(range(22, 26))
lExpected.extend(range(28, 32))
lExpected.extend(range(34, 36))

oRule.analyze(self.oFile)
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
Expand Down
46 changes: 28 additions & 18 deletions tests/variable/rule_400_test_input.fixed__align_left_no__align_paren_no.vhd
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,29 +1,39 @@
architecture rtl of fifo is

variable v_element : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
);

variable v : MY_TYPE := (
a => '0',
ddddd => (others => '0'),
ffff => (others => '0')
a => '0',
ddddd => (others => '0'),
ffff => (others => '0')
);

variable AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
w_data(DataRange_c),
w_strb(ByteRange_c));

variable AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
r_user(UserRange_c), b_user(UserRange_c),
r_data(DataRange_c));

begin

end architecture rtl;
46 changes: 28 additions & 18 deletions tests/variable/rule_400_test_input.fixed__align_left_no__align_paren_yes.vhd
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,29 +1,39 @@
architecture rtl of fifo is

variable v_element : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
);

variable v : MY_TYPE := (
a => '0',
ddddd => (others => '0'),
ffff => (others => '0')
a => '0',
ddddd => (others => '0'),
ffff => (others => '0')
);

variable AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
w_data(DataRange_c),
w_strb(ByteRange_c));

variable AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
r_user(UserRange_c), b_user(UserRange_c),
r_data(DataRange_c));

begin

end architecture rtl;
10 changes: 10 additions & 0 deletions tests/variable/rule_400_test_input.fixed__align_left_yes__align_paren_no.vhd
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,16 @@ architecture rtl of fifo is
ffff => (others => '0')
);

variable AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
w_data(DataRange_c),
w_strb(ByteRange_c));

variable AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
r_user(UserRange_c), b_user(UserRange_c),
r_data(DataRange_c));

begin

end architecture rtl;
10 changes: 10 additions & 0 deletions tests/variable/rule_400_test_input.fixed__align_left_yes__align_paren_yes.vhd
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,16 @@ architecture rtl of fifo is
ffff => (others => '0')
);

variable AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
w_data(DataRange_c),
w_strb(ByteRange_c));

variable AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
r_user(UserRange_c), b_user(UserRange_c),
r_data(DataRange_c));

begin

end architecture rtl;
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