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1. riscv-vip riscv-vip Public

   For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

   SystemVerilog 57 30

2. riscv-vip-scr1-demo riscv-vip-scr1-demo Public

   Demo of riscv-vip integration with the Syntacore SCR1 RISC-V core

   Shell 3 1

3. scr1 scr1 Public

   Forked from syntacore/scr1

   SCR1 is a high-quality open-source RISC-V MCU core in Verilog. This fork illustrates how the riscv-vip can be added to the testbench.

   SystemVerilog 1 1