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Update #3 Added a few tests.
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Next Steps: Will add a few more tests and then submit pull request
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jlb6740 committed May 13, 2020
1 parent 9a68ce4 commit 3bf2757
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Showing 4 changed files with 49 additions and 4 deletions.
1 change: 1 addition & 0 deletions cranelift/ben_simple.wat
Original file line number Diff line number Diff line change
Expand Up @@ -3,5 +3,6 @@
get_local 0
get_local 1
f32.add
get_local 1
)
)
1 change: 1 addition & 0 deletions cranelift/codegen/src/isa/x64/abi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -273,6 +273,7 @@ impl ABIBody for X64ABIBody {
// TODO do we need a sign extension if it's I32?
return Inst::mov_r_r(/*is64=*/ true, from_reg.to_reg(), to_reg);
} else if from_reg.get_class() == RegClass::V128 {
// TODO: How to support Movss. Should is64 always be true?
return Inst::sse_r_r(
/*is64=*/ true,
SSE_RM_R_Op::Movsd,
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17 changes: 13 additions & 4 deletions cranelift/codegen/src/isa/x64/inst/emit.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
use regalloc::Reg;

use crate::isa::x64::inst::*;
use regalloc::Reg;

fn low8willSXto64(x: u32) -> bool {
let xs = (x as i32) as i64;
Expand Down Expand Up @@ -763,7 +762,7 @@ pub(crate) fn emit<O: MachSectionOutput>(inst: &Inst, sink: &mut O) {
}
let mut flags = match size {
8 => F_NONE,
4 => F_CLEAR_REX_W,
4 | 2 => F_CLEAR_REX_W,
1 => F_CLEAR_REX_W | retainRedundantRex,
_ => panic!("x64::Inst::Cmp_RMI_R::emit: unreachable"),
};
Expand Down Expand Up @@ -1001,7 +1000,17 @@ pub(crate) fn emit<O: MachSectionOutput>(inst: &Inst, sink: &mut O) {
flags,
);
}
_ => unimplemented!("SSE_RM_R instruction"),
RM::M { addr } => {
emit_REX_OPCODES_MODRM_SIB_IMM_regG_memE(
sink,
LegacyPrefix::PfxF3,
opcode,
2,
regG.to_reg(),
addr,
flags,
);
}
}
}
_ => panic!("x64_emit: unhandled: {} ", inst.show_rru(None)),
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34 changes: 34 additions & 0 deletions cranelift/codegen/src/isa/x64/inst/emit_tests.rs
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,9 @@ fn test_x64_emit() {
let r14 = regs::r14();
let r15 = regs::r15();

let xmm0 = regs::xmm0();
let xmm1 = regs::xmm1();

// And Writable<> versions of the same:
let w_rax = Writable::<Reg>::from_reg(rax);
let w_rbx = Writable::<Reg>::from_reg(rbx);
Expand All @@ -51,6 +54,9 @@ fn test_x64_emit() {
let w_r14 = Writable::<Reg>::from_reg(r14);
let w_r15 = Writable::<Reg>::from_reg(r15);

let w_xmm0 = Writable::<Reg>::from_reg(xmm0);
let w_xmm1 = Writable::<Reg>::from_reg(xmm1);

let mut insns = Vec::<(Inst, &str, &str)>::new();

// ========================================================
Expand Down Expand Up @@ -2171,6 +2177,34 @@ fn test_x64_emit() {
"jmp *321(%r10,%rdx,4)",
));

// ========================================================
// SSE_RM_R

insns.push((
Inst::sse_rm_r(false, SSE_RM_R_Op::Addss, RM::reg(xmm1), w_xmm0),
"F30F58C1",
"addss %xmm1, %xmm0",
));
insns.push((
Inst::sse_rm_r(false, SSE_RM_R_Op::Subss, RM::reg(xmm0), w_xmm1),
"F30F5CC8",
"subss %xmm0, %xmm1",
));

insns.push((
Inst::sse_rm_r(
false,
SSE_RM_R_Op::Addss,
RM::mem(Addr::imm_reg_reg_shift(123, r10, rdx, 2)),
w_xmm0,
),
"F3410F5844927B",
"addss 123(%r10,%rdx,4), %xmm0",
));

// ========================================================
// SSE_R_R

// ========================================================
// Actually run the tests!
let flags = settings::Flags::new(settings::builder());
Expand Down

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