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plat-imx: psci: implement clock-gated cluster idle state #2
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jordanrh1
commented
Jun 12, 2018
- Implement WAIT mode with A7 clocks disabled
- Uses PSCI OS-initiated mode, extended state ID format, and ARM FFH
- Implement WAIT mode with A7 clocks disabled - Uses PSCI OS-initiated mode, extended state ID format, and ARM FFH
@@ -201,8 +201,52 @@ | |||
#error "CFG_MX6/7 not defined" | |||
#endif | |||
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/* SNVS */ |
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I think these definitions can be removed
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#define LPM_STATE_ALL_OFF \ | ||
(LPM_MODE_WAIT | LPM_STOP_ARM_CLOCK | LPM_POWER_DOWN_CORES | \ | ||
LPM_POWER_DOWN_SCU | LPM_POWER_DOWN_L2) |
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Not implemented. Remove
DMSG("ID = %d\n", id); | ||
if (id == 1) { | ||
if (soc_is_imx7ds()) | ||
return imx7d_lowpower_idle(power_state, entry, |
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imx7d_lowpower_idle [](start = 10, length = 19)
Where is this implemented?
#define LPM_POWER_DOWN_CORES BIT(3) | ||
#define LPM_POWER_DOWN_SCU BIT(4) | ||
#define LPM_POWER_DOWN_L2 BIT(5) | ||
#define LPM_INITIATING_CORE BIT(6) |
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All changes to this file probably need to move to cpuidle