set SRXISEL

kiffie · Feb 18, 2024 · 15f8d7b · 15f8d7b
1 parent b186538
commit 15f8d7b
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/pic32-hal/src/spi.rs b/pic32-hal/src/spi.rs
@@ -103,6 +103,7 @@ macro_rules! spi {
                             .mode16().bit(frame_format.mode16())
                             .ckp().bit(true)
                             .stxisel().bits(0b11) // IRQ when buffer not full
+                            .srxisel().bits(0b01) // IRQ when buffer is not empty
                             .msten().bit(true)
                             .on().bit(true)
                         });