The core of kivantium CPU.
- 2020/07/23 Restart project.
- 2020/07/24 RV32I is implemented (except
FENCE,ECALL,EBREAK)
This project is licensed under the terms of the MIT license.
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A RISC-V based CPU in SystemVerilog
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kivantium/kivantium-core
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A RISC-V based CPU in SystemVerilog
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