KUAN-YU CHEN

Summary

ECE PhD Candidate interested in Integrated Circuits industry, specialized in Accelerator Architecture

Education

• University of Michigan, Ann Arbor,Ph.D, Electrical and Computer Engineering (GPA:4.00/4.00)

  • Graduation Date : 01/2024
  • Relevant Courses :
    • EECS 573 Microarchitecture
    • EECS 579 Integrated Circuits Testing

• University of Michigan, Ann Arbor,M.S., Electrical and Computer Engineering (GPA:4.00/4.00)

  • Graduation Date : 04/2020
  • Relevant Courses :
    • EECS 427 VLSI Design I
    • EECS 470 Computer Architecture
    • EECS 523 Digital Integrated Technology
    • EECS 598 VLSI for Communication and Machine Learning
    • EECS 598 Accelerated Systems For AI And Health
    • EECS 627 VLSI Design II

• National Taiwan University (NTU) ,B.S., Electrical Engineering (GPA:4.15/4.30)

  • Graduation Date : 01/2018

Publications

2024

• P. Abillama et. al "A 22nm 9.51 TOPS/W Neural Engine with 2MB MRAM Leveraging Sparse-Orthogonal Walsh-Hadamard Transform Computations and Dynamic Power Gating," European Solid-State Electronics Research Conference (ESSERC), September 2024
• S. Choi et. al "ParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications," International Symposium on Low Power Electronics and Design (ISLPED), August 2024

2023

• A. Krishnakumar et. al "FALCON: An FPGA Emulation Platform for Domain-Specific Systems-on-Chip (DSSoCs)," IEEE Design & Test, 2023
• Y. Gu et. al "GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis," International Symposium on Computer Architecture (ISCA), June 2023

2022

• X. He et. al "Squaring the circle: Executing Sparse Matrix Computations on FlexTPU—a TPU-like processor," International Conference on Parallel Architectures and Compilation Techniques (PACT), Oct 2022
• L. Belayneh et. al "Locality-aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems," International Conference on Parallel Architectures and Compilation Techniques (PACT), Oct 2022
• N. Talati et. al "Mint: An Accelerator For Mining Temporal Motifs," International Symposium on Microarchitecture (MICRO), Oct. 2022
• T. Dunn et. al "SquiggleFilter: An Accelerator for Portable Virus Detection," MICRO Top Picks, IEEE MICRO, Issue 4, July-Aug 2022, Honorable Mention
• S. Feng et.al "MeNDA: A Near-Memory Multi-way Merge Solution for Sparse Transposition and Dataflows," International Symposium on Computer Architecture (ISCA), June 2022
• N. Talati et.al "NDMiner: Accelerating Graph Pattern Mining Using Near Data Processing," International Symposium on Computer Architecture (ISCA), June 2022
• K.-Y. Chen et.al "A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET," IEEE Symposium on VLSI Circuits (VLSI-Symp), June 2022
• D. Bliss et.al "Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor," International Symposium on Circuits and Systems (ISCAS), May 2022, Accepted as Lecture
• S. Kim et. al ”Versa: A 36-Core Systolic Multiprocessor with Dynamically-Reconfigurable Interconnect and Memory,” IEEE Journal of Solid State Circuits (JSSC), Volume: 57, Issue: 4, April 2022, pgs. 986-998
• C.-W. Tseng et. al "A Long-Range Narrowband RF Localization System with a Crystal-less Frequency Hopping Receiver," International Solid Stage Circuit Conference (ISSCC), Feb. 2022

2021

• T. Dunn et. al "SquiggleFilter: An Accelerator for Portable Virus Detection," International Symposium on Microarchitecture (MICRO), Oct. 2021
• S. Kim et. al ”Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm,” IEEE Symposium on VLSI Circuits (VLSI-Symp), June 2021

2020

• D.H. Park et. al ”A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator,” IEEE Journal of Solid State Circuits (JSSC), Vol. 55, No. 4, Jan 2020, pgs. 933-944

2019

• S. Pal et. al ”A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm,” IEEE Symposium on VLSI Circuits (VLSI-Symp), June 2019

Skills

• Programming Languages:

  • SystemVerilog
  • MATLAB
  • C
  • C++
  • Python

• Design Tools:

  • Design Compiler
  • Innovus
  • Calibre
  • Vivado
  • Virtuoso

Work Experiences

• Graduate Student Research Assistant (GSRA), University of Michigan, Ann Arbor

  • 01/2019 - 12/2023
  • Michigan Integrated Circuits Laboratory (MICL)
  • Advisor: Prof. David Blaauw

• Teaching Assistant, Department of Electrical Engineering, NTU

  • 02/2017 - 01/2018
  • EEE 5010 SoC Design Lab
  • EE 4039 Computer Architecture

• Intern,Chip Implementation Center, National Applied Research Laboratories, Taiwan

  • 07/2016 - 08/2016

Research Experiences (4 real silicon tape-out)

• Michigan Integrated Circuits Laboratory, University of Michigan

  • Advisor: Prof. David Blaauw

  • Lead Projects

    • DAP: Domain Adaptive Processor for ML & Wireless Communication
      • taped-out in GF 12nm process
      • accepted by 2022 VLSI-Symp
    • Reconfigurable FFT & FIR Accelerators with AXI compliance
      • Included in DASH-SoC

  • Collaborated Projects

    • DASH-SoC: Domain-Focused Advanced Software-Reconfigurable Heterogeneous SoC
      • taped-out in GF 12nm process 
    • Narrow Band Localization
      • taped-out in Fujitsu 55nm process
      • accepted by 2022 ISSCC
    • Transmuter: Software-Defined Reconfigurable Computer
      • taped-out in TSMC 28nm process
      • accepted by 2021 VLSI-Symp

Honors & Awards

• Presidential Awards,(Dean’s List) 2 times
• First Prize, 2017 Undergraduate Innovation Award
• Third Prize,2017 Integrated Circuits Design Contest
• Certificate of Outstanding Achievement,2016 Innovative Asia FPGA and SoC Design Contest
• Undergraduate Assistantship,TSMC