Skip to content
View kunalg123's full-sized avatar
đź’­
Open to Innovate !!
đź’­
Open to Innovate !!

Block or report kunalg123

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. vsdflow vsdflow Public

    VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using…

    Verilog 155 55

  2. icc2_workshop_collaterals icc2_workshop_collaterals Public

    This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for thes…

    Verilog 29 12

  3. riscv_workshop_collaterals riscv_workshop_collaterals Public

    This repository is created for conducting RISC-V 5-day workshops

    Coq 20 7

  4. flipflop_design flipflop_design Public

    This project has files needed to design and characterise flipflop

    19 3

  5. sky130RTLDesignAndSynthesisWorkshop sky130RTLDesignAndSynthesisWorkshop Public

    Verilog 11 12

  6. picorv32 picorv32 Public

    Forked from YosysHQ/picorv32

    PicoRV32 - A Size-Optimized RISC-V CPU

    Verilog 6 2